32 results about "Floating point dsp" patented technology

The invention relates to a SDINS/GPS integrated navigation system time synchronization method and synchronous data acquisition method. 1 PPS pulse of a GPS receiver is used as a reference to generate an IMU sampling clock, and the pulse signal outputted from the IMU is counted by a counter in the FPGA, so that IMP data sampling is synchronous with 1 PPS, and the synchronization of IMU data and GPS data is realized. GPS data is received through a serial port for realizing VHDL language. The floating point DSP responds the external interruption of the FPGA, reads the IMU data inside the FPGA, and acquires synchronous IMU data and reads GPS data in accordance with the IMU synchronization marks and GPS reading marks. The invention adopts hardware synchronization and time synchronization, leading to good stability. It can realize re-synchronization with 1 PPS, so as to provide high-precision synchronous data for integrated navigation computation and improve the overall performance of integrated navigation system. The DSP acquires synchronous data with interrupt mode and hardly occupies the DSP resource for computation, leading to good real-time performance.

A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability. The DSP core can perform operations on floating-point data in a complex domain and is capable of producing real and imaginary arithmetic results simultaneously. This capability allows a single-cycle execution of, for example, FFT butterflies, complex domain simultaneous addition and subtraction, complex multiply accumulate (MULACC), and real domain dual multiply-accumulators (MACs). The SoC may be programmed entirely from a microprocessor programming interface, using calls from a DSP library to execute DSP functions. The cores may also be programmed separately. Capability for programming and simulating the entire SoC are provided by a separate programming environment. The SoC may have heterogeneous processing cores in which either processing core may act as master or slave, or both cores may operate simultaneously and independently.

The invention provides a TMX320F28335 floating point DSP (Digital Signal Processor) based two-shaft photoelectric tracking system, belongs to the technical field of control of servo movement, and aims at solving the problems of low tracking precision and inconvenient mounting, dismounting and repairing due to the DSP based control for the two-shaft photoelectric tracking system in the prior art. The system comprises a detection device, a servo control module, an angle measuring loop module, a speed measuring loop module, a power amplification driving loop module, a communication loop module, an upper computer module and an image processing module; the angle position information and angle rate information measured by a photoelectric encoder and a gyro of the detection device are respectively sent to the servo control module through the angle measuring loop module and the speed measuring loop module; the image processing module is used for processing the acquired module to obtain the miss distance of a characteristics target; the servo control module is used for acquiring control quantity according to the angle position information, the angle rate information, the miss distance, an instruction of an upper computer and a set working mode and sending to the power amplification driving loop module to drive the detection device to track the characteristics target on real time. The system is applied to the field of military tracking.

The invention discloses a double-DSP control circuit of photovoltaic interconnected device with STATCOM function, which comprises the following parts: locating DSP chip, high-speed RAM chip, floating-point DSP chip, 16-bit FLASH chip, double-hole RAM chip, CPLD chip and signal adjusting circuit. The control circuit gathers each item electric quantity signal of photovoltaic signal, which generates PWM signal of control device interconnected inverter through combination calculation of signal disposal and two DSP. The double-DSP control circuit sends active power to electric net in the working time of photovoltaic interconnected device, which improves the utility of solar battery.

The invention discloses a Gaussian error function circuit applied to neural networks. The Gaussian error function circuit comprises three squarers, two multipliers, two multiplier-adders, two dot product digital signal processors, an adder, a derivation DSP, and an exponent DSP. The DSPs are Design Ware floating-point DSPs from Synopsys. The circuit has a simple structure, uses DSPs easy to obtain, and is easy to implement. Compared with the traditional Taylor expansion method implementation scheme, the circuit has very obvious advantages in terms of precision, area and speed, and especially, the precision is at least two orders of magnitude higher. Meanwhile, the circuit can be implemented using a Verilog code, and has nothing to do with any specific process, so that the circuit can be applied to different processes very easily and is of very strong portability. The Gaussian error function circuit can be applied to the design of various hardware circuits related to neural networks as a soft-core IP.

The invention provides a real-time controller of a universal frequency converter, which comprises a first floating-point DSP, a first dual-port RAM and a microprocessor, wherein the microprocessor is used for sending control command information to the first floating-point DSP via the first dual-port RAM; the operation information of the first floating-point DSP is sent to an upper machine via the first dual-port RAM; the first floating-point DSP is used for reading the external voltage signal and current signal and carrying out algorithm operation according to the voltage signal, the current signal and the control command information, and PWM control pulse is generated by the operation result to realize rectifier control. The real-time controller of the universal frequency converter has higher real-time property and low cost.

The invention discloses a low-carrier-wave-ratio on-line computation multi-mode space vector pulse width modulation soft core which can complete on-line computation multi-mode space vector pulse width modulation in a high-power three-phase alternating current asynchronous motor control system. The low-carrier-wave-ratio on-line computation multi-mode space vector pulse width modulation soft core mainly comprises an AD control module 01, a double-port RAM 02 based on FPGA, a double-port RAM control module 03, a section judgment module 04, a modulation mode switchover management module 05, an asynchronous modulation time computation module 06, a vector action angle computation module 07, a time normalization module 08 and a PWM signal generation module 09. The low-carrier-wave-ratio on-line computation multi-mode space vector pulse width modulation soft core not only has the advantages of high speeds and high reliability of a hardware circuit, but also has good module reusability and transportability, and is good in steady-state performance and dynamic-state performance. When serving as a motor control system coprocessor, the low-carrier-wave-ratio on-line computation multi-mode space vector pulse width modulation soft core liberates a core controller (a floating point DSP) from a large amount of sine and cosine computation and periodic events occupying too many resources, better runs a motor core control algorithm and improves the performance of the control system.

The present invention relates to a portable vibration controller adopting USB interface. Said portable vibration controller includes the following several portions: dual-channel data acquisition module, signal processing module, data storage module, signal output module, logic control module and USB communication module. Said invention is simple in structure and is high in accuracy.

The invention relates to a servo motion control device based on a floating-point DSP, which comprises a DSP unit circuit, a power circuit, a program memory circuit, a dual-port RAM circuit, a PC104 bus interface circuit, a board election control circuit, an orthogonal counter circuit, an I/O port expansion circuit, a servo interface circuit and a serial port control circuit. The invention can realize the high-precision motion control of the AC servo motor with the photoelectric encoder as the feedback through the software based on the floating-point DSP, including the angular position, angular rate, angular vibration and other motion modes, and not only can be used as the expansion board of the PC104 bus, but also can be used as the independent motion controller. Moreover, the invention has the advantages of high performance of real-time control, high flexibility of expansion and high control accuracy of the control system, and can be applied in the turntable system and servo platform of the field of the inertial navigation testing equipment and other fields requiring the accurate control of angular motion such as robots and the like.

The invention provides an Ethernet interface proposal for a high-speed floating point DSP processor aiming at characteristics thereof, and efficiently realizes the TCP/IP protocol on the DSP high-speed floating point processor. The technology comprises hardware logic design of an interface, bottom drive realization of an Ethernet adapter, realization of the TCP/IP protocol on the floating point DSP processor and communication program design of an upper computer. The technology solves the problem that the high-speed floating point DSP processor cannot carry out high-speed data transmission. The technology has strong universality, and is applicable to any floating point processor.

The invention relates to the design architecture of a multi-DSP parallel processing board based on a CPCI-E bus. The multi-DSP parallel processing board comprises four TS201 floating point DSPs and an XC7K325TFPGA, wherein each DSP is connected with the other three DSPs through full duplex LINK ports, and the four DSPs are connected with a FPGA through data buses and full duplex LINK ports. The PFGA is connected with a CPCI-Express bridge through a self-defined high-speed interface. According to the multi-DSP parallel processing board, electrified free switching is achieved for the LINK port loading mode of a TS201 array and the passive and active loading modes of the FPGA through the CPCI-E bus, high-speed data transmission of a DSP processing array is achieved through the serial difference characteristics of the CPCI-E bus and the external cache of the FPGA, and the multi-DSP parallel processing board has the advantages of being high in bus transmission speed, small in size, flexible in interface method, large in onboard cache and high in expansibility.

The invention discloses a temperature measuring method, comprising the following steps: (1) a high temperature optical lens picking up infrared radiation lights on a surface of a high temperature object, (2) transferring the infrared radiation lights to a control room through optical fibers, (3) in the control room inputting the optical fibers into a fiber bragg grating (FBG) optical grating through an input end of an Y type optical splitter, outputting the light reflected by the FBG optical grating through an output end of the Y type optical splitter and outputting to a detector (4), converting light signals reflected by each stage of the FBG optical grating into weak electronic signals by a corresponding avalanche photo diode (APD) infrared detector, inputting the electronic signals after regulated by a signal regulation circuit into an A/D conversion module of a high-speed floating point digital signal processor (DSP), (5) the high-speed floating point DSP performing filtration, colorimetric computation, temperature lookup, temperature fitting to the data of the A/D conversion module, and finally displaying the temperature in a curve manner on a liquid crystal displayer, thus the detection being more accurate and intuitive.

The invention discloses a 1PPS (pulse per second) latch which comprises a clock frequency multiplication module, a phase discriminator, a floating point DSP (digital signal processor), a two-order digital filter and a voltage-controlled oscillator. The satellite 1PPS and local 1PPS input by a receiver are subjected to phase discrimination; the phase difference output by the digital phase discriminator is subjected to data type conversion and then output to the two-order digital filter; the result output by the two-order digital filter is subjected to data type conversion and then output to the voltage-controlled oscillator; and the voltage-controlled oscillator generates local 1PPS. The invention also provides a control method using the latch.

The invention discloses a method for carrying out IPPS signal control, and the method comprises the steps: inputting a satellite IPPS signal and a local IPPS signal into a phase discriminator; carrying out the floating point DSP data type conversion of a phase difference value outputted by the phase discriminator into a floating point type; carrying out second-order digital filtering modeling through matlab, achieving a filter structure with the adjustable coefficient in a second-order digital filter based an FPGA through the VHDL language, and carrying out the smoothing filtering of the phase difference value of the floating point type; carrying out the floating point DSP data type conversion of an output value of the second-order digital filter into an integral type through a floating point DSP; outputting the integral data to a digital voltage-controlled oscillator through the floating point DSP; adjusting the IPPS output phase through the voltage-controlled oscillator according to the input data; enabling the IPPS signal outputted by the voltage-controlled oscillator to serve as an input signal, and feeding back the signal to the phase discriminator.

The invention discloses a frequency converter controller comprising the following parts of an SDRAM for buffering input signals and/or output signals; and an MCU connected to the SDRAM for processingthe input signals and/or output signals, wherein the MCU comprises a first floating point DSP and a second floating point DSP for algorithmically controlling the input signals and/or output signals; and a first CLA and a second CLA for logically controlling the input signals and/or output signals. It can be seen that by embedding two floating point DSPs and two CLAs in the MCU of the frequency inverter controller, the processing speed of the input signals and/or output signals of the controller can be greatly improved, and the buffering of the input signals and/or output signals by the SDRAM greatly improves the controller's throughput of interactive data, thereby solving the problems of slow data processing speed and low throughput during the data interaction process of the frequency inverter controller in the prior art.

The invention relates to a novel automatic device, and belongs to the technical field of automation. The novel automatic device comprises a protective CPU and a control CPU, wherein the protective CPU is used for completing the protection function of the automatic device, and the control CPU is used for completing the control function of the automatic device. A 32-bit floating point DSP TMS320C32 chip of the TI company is adopted in the protective CPU, a 32-bit Samsung S3C44B0X processor based on an ARM kernel is adopted in the control CPU, and the protective CPU and the control CPU are in communication connection through a dual-port RAM and a CPLD single chip microcomputer. The device is simplified, function repetition of some components is avoided, hardware resource waste is reduced, and reliability of the device is improved.