Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Multi-DSP parallel processing board based on CPCI-E bus

A parallel processing and bus technology, applied in instruments, computer control, simulators, etc., can solve the problems of no TS201 application, high technical level requirements, difficulties, etc., to save the number of external wiring, small size, fast transmission speed Effect

Inactive Publication Date: 2014-06-25
CHENGDU ZHIHENG BONA TECH
View PDF4 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] But at present, TS201 has not been applied to the processing board based on CPCI-E bus. The main reason is that TS201 and CPCI-E both have high technical requirements. It is more difficult to soften them together, and more comprehensive consideration is required More, it belongs to the problem of 1+1>2

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multi-DSP parallel processing board based on CPCI-E bus
  • Multi-DSP parallel processing board based on CPCI-E bus
  • Multi-DSP parallel processing board based on CPCI-E bus

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] Such as figure 2As shown, the multi-DSP parallel processing board (model BN904) based on the CPCI-E bus includes four TigerSharc201 (ie TS201) floating-point DSP processors from ADI and one Xilinx 7 series XC7K325T FPGA, each TigerSharc201 floating-point The DSP processors communicate with the other three TigerSharc201 floating-point DSP processors through the LINK port (ie figure 2 Each TigerSharc201 floating-point DSP processor is connected to the other three TigerSharc201 floating-point DSP processors through the LINK port, and the four TigerSharc201 floating-point DSP processors are connected to the full-duplex LINK port through the data bus. Connect with the FPGA of XC7K325T; the FPGA of the XC7K325T is connected to the CPCI-Express bridge through a custom high-speed interface, the CPCI-Express bridge is connected to the NP (network processor) through the parallel expansion port, and the FPGA of the XC7K325T is also connected to four TigerSharc201 floating-point...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to the design architecture of a multi-DSP parallel processing board based on a CPCI-E bus. The multi-DSP parallel processing board comprises four TS201 floating point DSPs and an XC7K325TFPGA, wherein each DSP is connected with the other three DSPs through full duplex LINK ports, and the four DSPs are connected with a FPGA through data buses and full duplex LINK ports. The PFGA is connected with a CPCI-Express bridge through a self-defined high-speed interface. According to the multi-DSP parallel processing board, electrified free switching is achieved for the LINK port loading mode of a TS201 array and the passive and active loading modes of the FPGA through the CPCI-E bus, high-speed data transmission of a DSP processing array is achieved through the serial difference characteristics of the CPCI-E bus and the external cache of the FPGA, and the multi-DSP parallel processing board has the advantages of being high in bus transmission speed, small in size, flexible in interface method, large in onboard cache and high in expansibility.

Description

technical field [0001] The invention relates to the field of high-speed digital signal communication processing, in particular to a multi-DSP parallel processing board based on CPCI-E bus. Background technique [0002] Most of the processing boards on the market are based on the traditional CPCI bus interface. CPCI belongs to the traditional parallel interface bus, which does not conform to the concept of serial transmission in modern communication. Not only is it large in size and complex in signal definition, but its transmission speed is only one tenth of that of the CPCI-E bus. Obviously, no matter how powerful the processing board is with this kind of interface, it will encounter the tight bottle of transmission and cannot give full play to its inherent advantages. Moreover, there is currently no processing board on the market that integrates high-end modules such as DDR3, Gigabit Network, Rapid IO, TigerSharc201, CPCI-E, and Xilinx 7 series FPGAs. At most, it realiz...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G05B19/042
Inventor 杜敏
Owner CHENGDU ZHIHENG BONA TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com