Unlock instant, AI-driven research and patent intelligence for your innovation.

Field programmable gate array loading method

A gate array, startup loading technology, applied in program control devices, instruments, electrical digital data processing, etc., can solve the problems affecting the startup speed of the system, long chip selection effective time, long loading time, etc., to reduce fault recovery time, Reduce startup time, improve product performance and metrics

Inactive Publication Date: 2008-02-27
HUAWEI TECH CO LTD
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the time for reading and writing FLASH is generally longer, the effective time of chip selection for each access to the EPLD register should also be longer
Moreover, the general data is loaded from the EPLD to the FPGA according to each BIT operation. When using this method to load, each time a BIT is loaded, the EPLD will be accessed at least 6 times (the above steps S6-S11), and a BYTE will be accessed. 48 times EPLD, when the loading file is very large (as the scale of internal resources continues to increase, the loading file is also increasing), it will cause the loading time to be too long, which will affect the startup speed of the entire system

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Field programmable gate array loading method
  • Field programmable gate array loading method
  • Field programmable gate array loading method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0032] See also Fig. 4 to Fig. 6, be a preferred embodiment of the loading method of field programmable gate array of the present invention, at first as Fig. 4, erasable programmable logic device EPLD14 is set between CPU11 and field programmable gate array FPGA13 . The CPU11 is connected to the EPLD14 and the FLASH12 through the bus, so as to quickly load the required loading files stored in the FLASH12 into the FPGA13 through the EPLD14. The EPLD14 is provided with a control register 31, an 8-bit loading data register 32 and a clock output logic 33, and an external working clock 142 is added to the EPLD14. Described control register 31 is connected with the control signal pin (nCONFIG, DONE, STATE) of FPGA13, and described loading data register 32 is connected with the data input pin of FPGA13, and described clock output logic 33 is connected with the clock input pin of FPGA13 connect.

[0033]As shown in FIG. 5 , when loading is required, the loading is first started (S5-...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Disclosed is a method for loading field programmable gate array, which comprises steps of: placing EPLD between CPU and FPGA; S5-1: starting to load; S5-2: detecting whether the loading is over or not, that is, stopping loading by judging the DONE signal of FPGA as end, and when judging the DONE signal of being not over, executing following steps: S5-3, S5-4: Writing one byte data needed for loading into the loading data register of the EPLD once by CPU; S5-5: completing the loading of needed data to the FPGA by the internal logic of the EPLD; S5-6: delaying some time; repeating the S5-2 to S5-6 until finishing loading.

Description

technical field [0001] The present invention relates to a method for loading files into field-programmable gate arrays (FPGA, field-programmable gate arrays), in particular to a method for loading files to FPGA using an erasable programmable logic device (EPLD, erasable programmable logic device). Background technique [0002] A Field Programmable Gate Array (FPGA) is an erasable programmable read-only memory. Usually, when the board is powered on and initialized, relevant programs and data are loaded into the FPGA. After the FPGA is initialized, complex logic control can be completed to realize various business processing functions. Since the FPGA is a logic chip that does not save data when it is powered off, it is required to reload every time it is powered on, that is, to rewrite the data into the FPGA chip so that it can work normally. [0003] The loading method of an existing field programmable gate array is to store the files to be loaded in the flash memory (FLASH,...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/44G06F12/00
Inventor 祝文刚
Owner HUAWEI TECH CO LTD