5results about How to "Write less" patented technology

The invention discloses a grid control field sequence circuit and method, and the circuit comprises M rows of sub-circuits, each sub-circuit comprises a compensation unit, and each compensation unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a pre-storage capacitor. A first source-drain electrode of the first transistor is coupled to a positive power line, and a second source-drain electrode of the first transistor is coupled to a second source-drain electrode of the second transistor and a first source-drain electrode of the third transistor; a first source drain electrode of the second transistor is coupled to a grid electrode of the third transistor and one end of the pre-storage capacitor; the second source electrode of the third transistor of the sub-circuit of the Nth row is coupled to the first source drain electrode of a fourth transistor, and the second source drain electrode of the fourth transistor is coupled to a data signal line. The beneficial effects of the invention are that the threshold voltage is written in advance by using the conduction characteristic of the transistor, thereby avoiding the image abnormity phenomenon caused by the drift of the threshold voltage.

The log collection method and system provided in this specification builds a target Pod, mounts the pre-set target directories in multiple application Pods on the physical machine to the created target Pod, and takes over the writing and collection of log data of all target logs under the target directory. The target Pod writes the log data of all application Pods into a target file, and then writes the target logs in the target file into the storage path corresponding to the application Pod in sequence according to the classification of the application Pod to which they belong, so that random writes to the storage device become sequential writes, greatly improving the write performance.

The invention relates to the technical field of intelligent building elevator control, in particular to an off-line elevator calling control method based on edge service, comprising an elevator control system with cloud center service and local edge service, the off-line elevator calling control method comprises the following steps: S1, a user initiates an elevator calling request, s2, when the elevator control system is disconnected from the cloud center service, the working mode is switched to an offline mode; s3, the elevator control system carries out local right judgment; s4, the elevator control system inquires the authority information through the local edge service and verifies whether the user has the authority to access the target floor in combination with the floor information of the local database, and S5, the elevator control system determines the elevator calling type according to the elevator calling request and finally executes the elevator calling operation according to the elevator calling type. According to the invention, when the central service is not available, elevator operation such as elevator calling can still be completed, and normal use of the elevator system is ensured.

The application provides a data processing device, a data processing method and related devices, comprising a neural network processor, first, according to the channel number n of the first data, the first data is divided into n first sub-data, the first data represents data to be stored, n is a positive integer less than or equal to M / 2; each first sub-data is written into a circular cache space composed of INT(M / n) ring cache space groups, and any one circular cache space is used for storing any one first sub-data. The area of the cache control circuit in the neural network processor can be reduced by a specific storage space architecture, and the power consumption of data writing and reading is reduced.

The invention discloses a flash memory structure and a forming method thereof. The structure comprises a substrate; the two storage gate structures are located on the substrate and are separated from each other, an opening is formed between the two storage structures, each storage gate structure comprises a floating gate, a control gate dielectric layer located on the floating gate and a control gate located on the control gate dielectric layer, each floating gate is provided with a first side wall exposed by the opening, and each control gate is provided with a second side wall exposed by the opening. The first side wall is of a corrugated structure, the corrugated structure comprises a plurality of protruding parts, the protruding parts are arranged in the direction perpendicular to the surface of the substrate, and the bottom size of each protruding part is larger than the top size of each protruding part; the erasing gate structure is positioned in the opening; the word line structures are located on the two sides of the storage gate structure and the erasing gate structure respectively, and the erasing efficiency of the formed flash memory structure is improved.