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Baseband radio frequency interface based on software defined radio (SDR) and application method thereof

A software radio and radio frequency interface technology, applied in wireless communication, electrical components, transmission systems, etc., can solve the problems of large baseband radio interface buffer, occupy a large area, and complex circuits, and achieve low delay, strong pertinence, and circuit simple structure

Active Publication Date: 2012-10-17
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The baseband radio frequency interface AIF of TI keystone multi-core DSP is powerful, but because it needs to support up to six wireless communication modes, its internal FIFO will be very large, and it also includes general paket mode DMA, etc., so the circuit is very complicated. and a large area
[0007] It can be seen that there are certain defects in the above two existing implementation methods, that is, the circuit is very complicated, resulting in a large area occupied, so that the power consumption is also large, and at the same time, the buffer required by the baseband radio frequency interface is also large

Method used

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  • Baseband radio frequency interface based on software defined radio (SDR) and application method thereof
  • Baseband radio frequency interface based on software defined radio (SDR) and application method thereof
  • Baseband radio frequency interface based on software defined radio (SDR) and application method thereof

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Embodiment 1

[0082] Figure 4 A block diagram of the downlink data processing flow of the baseband radio frequency interface of the present invention, such as Figure 4 As shown, the baseband radio interface is based on the base clock of the RFC, and samples one data according to the configured sampling interval, such as every clock cycle, or two, four, eight or sixteen clock cycles, etc., the sampled data passes through the fixed point After the conversion to floating point (Fixed to Flating-point), it is stored in the Ping-Pong Buffer. When it is full of 8 data, that is, 256bits, that is, it is full. Figure 4 After buffering Buf0 or buffering Buf1 in the buffer, a write request is issued to the vector processor.

[0083] Figure 4 The Write_Ptr is the address written into the Ping-Pong Buffer, with 32bits of data, that is, a pair of iq data as the unit, Write_Ptr[3:0] is 4bits wide, representing 0 to 15 32bits data, a total of two 256bits, That is, a total of sixteen 32bits data are ...

Embodiment 2

[0087] Figure 5 It is a block diagram of the upstream data processing flow of the baseband radio frequency interface of the present invention, such as Figure 5 As shown in the figure, under the timing of the uplink frame, the baseband radio interface sends a read request to the vector processor. After reading 256bits of data each time, it is stored in the buffer Buf0 or buffer Buf1 in the ping-pong Buffer, and then the data in the buffer is taken out eight times. After the floating-point to fixed conversion (Flating-point To Fixed), the data is sent to the RFC according to the timing information given by the RFC.

[0088] Figure 5 The Write_Buf_sel described in the ping-pong buffer indicates which buffer to write the uplink data into. For example, 0 indicates that the buffer is written to Buf0, and 1 indicates that the buffer is written to Buf1. RFC, the Read_Ptr[3:0] is 4 bits wide, indicating 0 to 15 pieces of 32bits data, that is, 16 pieces of 32bits data; the tx_idata...

Embodiment 3

[0091] Image 6 It is a schematic diagram of the downlink events of the baseband radio interface of the present invention, taking the LTE mode as an example, such as Image 6 As shown, the two arrows in the upper part represent the frame timing, and the lower part is a schematic diagram of the event time generated by the event table. In the normal (normal) mode of the LTE mode, 13 symbol events are generally generated between two subframe events; in the extended (Extend) mode, 11 symbol events are generally generated between two subframe events. The event timing lags behind the frame timing by about 1 symbol, that is, the vector processor is started at each event moment, and the vector processor processes the received antenna data or other tasks.

[0092] Image 6 The hw_rx_sf described in represents the subframe boundary of hardware downlink; the Sym0 / event_sf represents the end position of the 0th symbol and the subframe boundary of the event table we defined, because the ...

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Abstract

The invention discloses a baseband radio frequency interface based on a software defined radio (SDR). The baseband radio frequency interface based on the SDR comprises an uplink data processing module, a downlink data processing module corresponding to different communication modes, an uplink event list module, a downlink event list module, a configuration register, a selector and a communication module. The invention also discloses an application method of the baseband radio frequency interface based on the SDR. Through using the baseband radio frequency interface and the application method, the baseband radio frequency interface can be guaranteed to possess versatility and simultaneously possess advantages of a simple circuit and low power consumption. Scheduling to a vector processor or a multi-core DSP can be simply realized.

Description

technical field [0001] The invention relates to the field of software radio, in particular to a software radio-based baseband radio frequency interface and an application method thereof. Background technique [0002] With the development of wireless communication technology, multiple modes of communication systems have appeared. In order to meet the interoperability problem of different modes, the concept of Software Defined Radio (SDR) has been proposed. The central idea of ​​software radio is to construct a general hardware platform with openness, standardization and modularization, realize various functions of communication through software, and make broadband analog / digital (A / D) converters and digital / analog The (D / A) converter is as close as possible to the antenna to develop a new generation of wireless communication systems with high flexibility and openness. Because the software radio can add new functions by adding software modules, and the hardware can also be co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04W92/00
CPCH04B1/0003H04W92/00
Inventor 林文琼肖海勇陈宁
Owner SANECHIPS TECH CO LTD
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