Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Nonvolatile semiconductor memory device

A storage device, non-volatile technology, applied in the direction of semiconductor devices, information storage, static memory, etc., can solve the problems of excessive erasure, increase of memory unit occupied area, conflict of processing size limit, etc., and achieve the goal of increasing data rewriting times Effect

Inactive Publication Date: 2007-04-04
PANASONIC CORP
View PDF0 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The nonvolatile memory element using the standard CMOS process of the above-mentioned prior art has the following problems: after the writing speed is increased at a high speed, the occupied area of ​​the memory cell is increased; Conflict over minimum process size limits for gate-eliminated transistors that make up memory cells
[0011] In addition, in order to increase the speed of writing and erasing, the capacity of the control gate transistor must be larger than that of the read transistor, but the threshold voltage of the state of charge 0 (extreme state after reliability degradation) is lowered.
In this way, in order to take advantage of the advantages of the differentially amplified memory cell with excellent data retention, it is necessary to set the threshold voltage of the erasing state to be extremely low, which easily causes the problem of excessive erasing.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Nonvolatile semiconductor memory device
  • Nonvolatile semiconductor memory device
  • Nonvolatile semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach 》

[0068] FIG. 7 shows a circuit diagram of the nonvolatile memory element in the first embodiment of the present invention, and FIG. 8 shows its cross-sectional view. The nonvolatile memory element of the present invention is composed of three transistors in which the control gate transistor 24 is PMOS, the readout transistor 26 is NMOS, and the erasing gate transistor 25 is N-type DMOS. , called "PMOS-NMOS-DMOS (PND) unit".

[0069] In Fig. 7, 27 is the control gate (CG), 28 is the elimination gate (EG), 29 is the drain terminal of the NMOS transistor, 30 is the source terminal of the NMOS transistor, 31 is the P-type silicon substrate terminal, and 32 is the floating Gate (FG). In FIG. 8, 33 and 34 are N-type well regions, and 35 is a P-type silicon substrate. The polysilicon gates of PMOS 24 , NMOS 26 , and N-type DMOS 25 are electrically connected to form floating gate (FG) 32 of the nonvolatile memory element. The N-type well region 34 of the PMOS 24 serves as the contro...

no. 2 Embodiment approach 》

[0074] FIG. 11 is a circuit diagram of a nonvolatile semiconductor memory device configured with differential cells in a second embodiment of the present invention. One of the differential bit units is called a T (True) bit, and the other is called a B (Bar) bit. Here, 45 is a T-bit control gate transistor (PMOS transistor), 46 is a T-bit erasing gate transistor (N-type DMOS transistor), 47 is a T-bit readout transistor (NMOS transistor), and 48 is a load PMOS transistor. Transistor, 49 is the control gate transistor (PMOS transistor) of B bit, 50 is the elimination gate transistor (N-type DMOS transistor) of B bit, 51 is the readout transistor (NMOS transistor), 52 is the load PMOS transistor, 53 is Bit line (BL), 54 is a bit line bar ( / BL), and 55 is a sense amplifier.

[0075] 12 is a circuit diagram showing an operation of writing "1" in the configuration of the differential unit in the second embodiment of the present invention. In the operation of writing "1" in the di...

no. 3 Embodiment approach 》

[0082] FIG. 15 shows a circuit diagram of a nonvolatile memory element in a third embodiment of the present invention. Here, 89 is a program gate transistor (PMOS transistor), 90 is a control gate transistor (PMOS transistor), 91 is an erasing gate transistor (PMOS transistor), 92 is a readout transistor (NMOS transistor), and 93 is a program gate transistor. 94 is the control gate (CG), 95 is the elimination gate (EG), 96 is the drain terminal of the NMOS transistor, 97 is the source terminal of the NMOS transistor, 98 is the P-type silicon substrate terminal, 99 is the floating gate (FG).

[0083] FIG. 16 shows a cross-sectional view of a nonvolatile memory element in a third embodiment of the present invention. Here, 100, 101 and 102 are N-type well regions, and 103 is a P-type silicon substrate. In a 3-transistor type nonvolatile memory element, the nonvolatile memory element is constituted by adding 4 transistors with a program gate as another control gate.

[0084] In...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Login to View More

Abstract

A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate (32) includes: a plurality of MOS transistors (24, 25, 26) sharing the floating gate (32). In the device, a PMOS (24) is used for coupling during writing and an n-type depletion MOS (DMOS) (25) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS (24) is used for writing and coupling of depletion capacitance by the n-type DMOS (25) is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor memory device, and more specifically, the present invention relates to a low-cost nonvolatile semiconductor memory device that can be incorporated into an LSI of a cutting-edge standard CMOS process. Background technique [0002] In recent years, in the system LSI of the advanced standard CMOS process, there has been an increasing demand for mounting security information centering on content-based encryption keywords. For this installation, the use of metal fuses is being studied. But worry about information leakage after being parsed. As a solution to this problem, a low-cost rewritable nonvolatile semiconductor storage device has been considered. [0003] When a nonvolatile semiconductor storage device such as a flash memory is mounted on a system LSI, a separate special process is required compared to the standard CMOS process, so the process cost increases, and a cutting-edge process ca...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G11C16/04G11C11/56H01L27/115H01L27/105
Inventor 山本安卫县泰宏白滨政则川崎利昭
Owner PANASONIC CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com