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Integrated circuit elements and byte erase method

A technology of integrated circuits and bytes, applied in information storage, static memory, instruments, etc., can solve the problems of general products without structure and inconvenience

Active Publication Date: 2008-10-01
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] This shows that above-mentioned existing integrated circuit element and the method for erasing of byte obviously still have inconvenience and defect in structure and use, and urgently need to be further improved
In order to solve the problems existing in the method of erasing integrated circuit components and bytes, relevant manufacturers have tried their best to find a solution, but for a long time, no suitable design has been developed, and there is no suitable solution for general products. The structure can solve the above-mentioned problems, which is obviously a problem that relevant industry players are eager to solve

Method used

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  • Integrated circuit elements and byte erase method
  • Integrated circuit elements and byte erase method
  • Integrated circuit elements and byte erase method

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Embodiment Construction

[0043] In order to further illustrate the technical means and effects that the present invention adopts for reaching the predetermined invention purpose, below in conjunction with the accompanying drawings and preferred embodiments, its specific implementation of the flash memory with byte erasing proposed according to the present invention , structure, feature and effect thereof, detailed description is as follows.

[0044] A detailed description of embodiments of the invention will be provided in Figure 1 to Figure 6 middle.

[0045] see figure 1 Shown is a block diagram of an integrated circuit supporting byte erase and vertical pages according to the present invention. The integrated circuit includes a memory array 100 implemented using NROM memory cells and supporting vertical pages. In some instances, memory array 100 is naturally or logically assembled as follows figure 2 and image 3 depicted. In the memory array 100, a page / row decoder 101 is coupled to a plur...

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Abstract

A process and a memory architecture is based on ''vertical'' pages, and support byte by byte erasure. A byte within a ''vertical'' page is erased, and then other bytes within the ''vertical'' page sharing bit lines with the erased byte, are subjected to a program verify operation after exposure to the stress caused by the erase process. The other bytes in the page are re-programmed to recover the data if they fail verify. Therefore, byte erase is executed without the erase / re-program cycling, and only memory cells within the same vertical page as the erased byte, which suffer stress from the erase potentials on the shared bit lines sufficient to shift their thresholds out of range, are re-programmed.

Description

technical field [0001] The present invention relates to an electrically programmable and erasable non-volatile memory (electrically programmable and erasable non-volatile memory) and an integrated circuit containing the memory, in particular to the device structure supporting byte erasing ) IC device and byte erase method. Background technique [0002] Electronic programmable erasable non-volatile memory (memory is memory, storage, hereinafter referred to as memory) technology includes flash memory (flash memory, flash memory is flash memory, hereinafter referred to as flash memory) body) is suitable for a variety of applications. Technologies based on floating gates such as standard Electronically Erasable Programmable Read-Only Memory (EEPROM) or charge trapping layers such as oxide-nitride-oxide Oxide-nitride-oxide memory cells Nitride Read-Only Memory (NROM) are usually programmable and erased many times. In typical flash memory technology, the erase process is perfor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/16G11C16/00G11C16/34
CPCG11C16/344G11C16/16
Inventor 洪俊雄张钦鸿
Owner MACRONIX INT CO LTD