System and method for quad-pumped address bus

Abstract

A microprocessor interface system includes a system bus with a bus clock and a quadruple frequency address signal group, and a plurality of devices coupled to the system bus. Each device executes a quadruple frequency processing program on the system bus. During each phase of the bus clock cycle, a plurality of request packets are successively transmitted from the system bus through the address signal group, and the device includes at least one microprocessor and One or more bus media, in a specific embodiment, when transmitting the first and second request packets, the first address data is multiplexed into the address signal group during the first phase of the bus clock cycle, and the third and the fourth request packet, the second address data is multiplexed into the address signal group during the second phase of the bus clock cycle.

Description

technical field [0001] This case cites priority to: U.S. Provisional Application No. 60 / 698,150, filed July 11, 2005; and U.S. Formal Application No. 11 / 369,896, filed March 7, 2006. [0002] The US applications to which this application is based are related to the following co-pending US patent applications, which have a common assignee and at least one common inventor. [0003] serial number submission date Invention name 60 / 700691 2005 / 07 / 19 APPARATUS AND METHOD FOR SPARSE LINE WRITE TRANSACTIONS 60 / 696702 2005 / 07 / 05 MICROPROCESSOR APPARATUS ANDMETHOD FOR ENABLING VARIABLE WIDTH DATA TRANSFERS 60 / 698149 2005 / 07 / 11 FLEXIBLE WIDTH DATA PROTOCOL 60 / 700692 2005 / 07 / 19 APPARATUS AND METHOD FORO RDERING TRANSACTION BEATS IN A DATA TRANSFER [0004] The present invention relates to a kind of processor address bus, especially a kind of device and method for address bus of quadruple-pumped / double-pumped, in order to solve the prob...

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Problems solved by technology

[0006] The inventors have noticed that this group structure of address signals is problematic in some applications where the packet size and / or energy are limited. Furthermore, each time one of the signals is driven onto the bus, such as at a given clock Multiple generation processes within a cycle will consume additional energy. Therefore, it is desirable to provide a mechanism to reduce the number of address signal group pins and their corresponding energy requirements. However, the function of the address still reserved

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