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Chip encapsulation structure

A chip packaging structure and chip technology, which is applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problem of offset or fracture of the third bonding wire, and achieve the effect of reducing the volume

Active Publication Date: 2009-03-18
CHIPMOS TECHSHANGHAI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In other words, the height of the third bonding wire 134 is relatively high, so during the process of filling the encapsulant 140 , the encapsulant 140 may easily cause the third bonding wire 134 to shift or break.

Method used

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  • Chip encapsulation structure
  • Chip encapsulation structure
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Examples

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Embodiment Construction

[0023] image 3 is a schematic side view of a chip package according to an embodiment of the present invention. Figure 4 yes image 3 A schematic top view of the chip package. For the convenience of explanation, image 3 and Figure 4 is a perspective view of the encapsulant 240 , and only outlines of the encapsulant 240 are drawn with dotted lines. The chip packaging structure 200 includes a lead frame 210 , a chip 220 , at least one first bonding wire 230 , at least one second bonding wire 232 , a plurality of third bonding wires 234 and an encapsulant 240 .

[0024] The lead frame 210 includes a chip holder 212 , a plurality of inner leads 214 and a bus bar 216 . The inner pins 214 are disposed on the periphery of the chip holder 212 , wherein the inner pins 214 include at least one first inner pin 214 a and a plurality of second inner pins 214 b. The bus bar 216 is interposed between the die holder 212 and the inner lead 214 , and the bus bar 216 maintains a first h...

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PUM

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Abstract

The utility model discloses a chip packaging structure, which comprises a lead holder, at least a first weld wire, at least a second weld wire, a plurality of third weld wire and a packaging colloid; wherein, the lead holder comprises a chip base, a plurality of inner pins and at least a bus bar; the inner pins are arranged at the external periphery of the chip base, the bus bar is arranged between the chip base and the inner pins. Height difference is maintained between the bus bar and the inner pins; the bus bar is designed in a settlement manner. The chip is arranged on the chip base, and comprises at least a first contact and a second contact; the first weld wire is connected between the first contact and the bus bar; the second weld wire is connected between the bus bar and one of the inner pins; the third weld wire is connected between other inner pins and the second contact. The packaging colloid covers the chip base, the inner pins, the bus bar, the chip, the first weld wire, the second weld wire and the third weld wires.

Description

technical field [0001] The present invention relates to a chip packaging structure, and in particular to a chip packaging structure with bus bars. Background technique [0002] In the semiconductor industry, the production of integrated circuits (IC) can be mainly divided into three stages: IC design, IC process, and IC package. [0003] In the fabrication of integrated circuits, chips are completed through the steps of wafer fabrication, integrated circuit formation, and wafer sawing. The large chip has an active surface, which generally refers to the surface of the large chip with active devices. After the integrated circuit inside the large chip is completed, the active surface of the large chip is also equipped with a plurality of bonding pads, so that the chips formed by cutting the large chip can be electrically connected to the outside through these bonding pads. carrier. The carrier is, for example, a leadframe or a package substrate. The chip can be connected to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/495H01L23/49
CPCH01L2224/4911H01L24/49H01L2924/01082H01L2224/48091H01L2224/32245H01L2224/48247H01L2224/73215H01L2924/19107H01L2924/14H01L2924/181H01L2224/05554H01L2224/49H01L2924/00014H01L2924/00H01L2924/00012
Inventor 吴燕毅李欣鸣黄志龙
Owner CHIPMOS TECHSHANGHAI
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