Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL

A compressor and adiabatic technology, applied in the direction of logic circuits using basic logic circuit components, calculations using number system representations, calculations using non-number system representations, etc., can solve the problems of irreversibility from electric energy to heat energy, and non-recoverable energy , to achieve the effect of connection and area reduction

Inactive Publication Date: 2010-01-13
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the traditional CMOS integrated circuit is powered by a DC power supply, its energy loss is mainly caused by the irreversibility of electric energy to heat energy and the irreversible energy recovery when charging and discharging the node capacitance

Method used

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  • Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL
  • Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL
  • Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL

Examples

Experimental program
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Effect test

Embodiment 1

[0029] Embodiment one: if Figure 5 and Image 6 As shown, a CTGAL-based adiabatic 4-2 compressor is composed of four 4-2 compression units 1 connected in series. The 4-2 compression unit includes a high-order carry signal generation circuit 11 and a next-stage carry signal generation circuit 12 The summation signal generating circuit 13, the high-order carry signal generating circuit 11 is composed of two clocked transmission gate adiabatic logic OR gate circuits and one clocked transmission gate adiabatic logic AND gate circuit, and the next stage carry signal generating circuit 12 is composed of two A clocked transmission gate adiabatic logic AND gate circuit, a clocked transmission gate adiabatic logic OR gate circuit and a clocked transmission gate adiabatic logic two-to-one selector, the summation signal generation circuit 13 is composed of four clocked transmission gates adiabatic logic Exclusive OR gate circuit, the output end of the second stage clocked transmission ...

Embodiment 2

[0031] Embodiment two: if Figure 7 and Figure 8 As shown, the 4×4 multiplier using the same adiabatic 4-2 compressor as in Embodiment 1 includes an adiabatic summation and array 10, an adiabatic 4-2 compressor 20 and an adiabatic parallel prefix adder 30, The adiabatic summation AND array 10 includes sixteen independent clocked transmission gate adiabatic logic AND circuits, and the adiabatic parallel prefix adder 30 is an 8-bit Ladner-Fischer adder based on clocked transmission gate adiabatic logic.

[0032] The Wallace tree based on the adiabatic 4-2 compressor can reduce the delay time series of the entire array from 0(n / 2*d) of the serial addition array to 0((log 2 n)*d), wherein, n is the number of partial products, and d is the delay time of a 4-2 compressor. Depend on Figure 8 , Figure 9 It can be seen that when there are 16 partial products, the delay time of the serial addition whole column is the delay time of the seven-stage adiabatic 4-2 compressor and the ...

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Abstract

The invention discloses an adiabatic 4-2 compressor based on CTGAL and a 4*4 multiplier formed by using the adiabatic 4-2 compressor. A carry signal input end Cin of a high adiabatic 4-2 compressor neighboring the standard adiabatic 4-2 compressor is accessed into a high carry signal output end Cout of the standard adiabatic 4-2 compressor; as a two-phase non-overlapping power clock is adopted by the CTGAL, the operation of an adiabatic 4-2 compressing unit circuit is divided into three grades; therefore, the standard Cout and the neighboring high Cin have the same phase position relation and correct logic calculation can be achieved; besides, compared with the traditional 4-2 compressor based on CMOS under the same situation of using an adiabatic circuit to realize, as a selector and an exclusive or gate of the invention have the same circuit structure, the timelag, the links and the area of the circuit are all relatively reduced; the energy consumption can be saved by 90 percent; as the adiabatic circuit has extremely low power consumption, the multiplier of the invention can realize a relatively lower power consumption.

Description

technical field [0001] The invention relates to a multiplication circuit, in particular to a CTGAL-based adiabatic 4-2 compressor and 4×4 multiplier. Background technique [0002] In the existing VLSI of deep submicron process, low power consumption has become one of the primary considerations in chip design. Research on low power consumption technology has become an increasingly important field in integrated circuit design. Multiplication is the most basic arithmetic operation. The multiplier is a key component of modern microprocessors. It plays an important role in many fields and largely affects the power consumption of the system. For example, it is mainly composed of multipliers. The power consumed by the multiply-adder unit usually accounts for 50% of the power consumption of the entire DSP chip. Therefore, it is of great significance to study low-power multipliers. Since the traditional CMOS integrated circuit is powered by a DC power supply, its energy loss is ma...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): G06F7/52G06F7/60H03K19/173
Inventor汪鹏君徐建
OwnerNINGBO UNIV