Dithering cache regulation means for circuit simulation system
A technology of jitter buffering and circuit simulation, applied in transmission systems, digital transmission systems, electrical components, etc., can solve problems such as transmission quality degradation, TDM service transmission quality degradation, interruption, etc., to achieve unaffected clock transmission quality and optimize TDM The effect of transmission quality and simplification of operation process
Active Publication Date: 2010-12-08
ZTE CORP
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Problems solved by technology
These methods are not technologies for automatically adjusting the jitter buffer, which may easily cause the transmission quality of TDM services to decline or even be interrupted, or the delay is too large due to the excessive setting of the jitter buffer, and the transmission quality will be reduced.
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[0027] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. For convenience of description, the packet switching network is referred to as the network for short below.
[0028] Such as image 3 As shown, the jitter buffer adjustment method of the CES system of the present invention comprises the following steps:
[0029] Step 101: Setting and initializing the jitter buffer of the CES system.
[0030] After the service is connected, the destination end obtains the PDV of the network, and then sets the initial jitter buffer length. Here, service connectivity means that the gateway and intermediate nodes of the network are configured correctly so that TDM data frames can be encapsulated into packets via the source end, and then the TDM data frames can be recovered by the destination end through the packet network. After the service is connected, both the source end and the destination end can co...
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The present invention discloses a dithering buffer adjustment method in a circuit simulating system including procedures below: Dithering buffering in a preset period is monitored to observe existence of quite higher or lower time-delay dithering of a group-based exchange network. As the time-delay dithering exceeds an upper dithering threshold, it is necessary to reset a new dithering buffer depth and an upper and a lower dithering threshold to increase the dithering buffer. While the time-delay dithering is lower than the lower dithering threshold, it needs to reset a new dithering buffer depth and a new upper and a lower dithering threshold to decrease the dithering buffer. As the time-delay dithering ranges between the upper threshold and the lower threshold, a next preset period is monitored. The method arranges dithering buffer variation to realize automatic adjustment according to variations of network time-delay dithering, makes the time-delay dithering led in by the group-based exchange network absorbed at most and optimizes the time delay led in the dithering buffer.
Description
technical field [0001] The invention relates to the field of circuit emulation (CES, Circuit Emulation Service), in particular to a jitter buffer adjustment method of a circuit emulation system. Background technique [0002] With the popularization of IP technology, it is becoming more and more a trend of network technology development to carry multiple services on the packet switching network. One of the typical services is to use the packet switching network to transmit the traditional Time Division Multiplexing (TDM, Time Division Multiplexing) The technology used by various circuit services in the network is CES technology. [0003] The basic principle of CES technology is as follows: figure 1 As shown, this technology builds a channel on the packet switching network (PSN, Packet Switch Network). By adding a header at the source end, each TDM data frame is encapsulated with a packet, and then transmitted to the destination through the channel built in the packet switchi...
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IPC IPC(8): H04L1/00H04L12/56H04L12/26H04L49/9023
Inventor 张宏熙李明生
Owner ZTE CORP