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Integrated transistor device and corresponding manufacturing method

A technology of transistors and devices, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems such as no solution found

Inactive Publication Date: 2008-03-12
QIMONDA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, a satisfactory solution that is easily implemented has not been found so far

Method used

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  • Integrated transistor device and corresponding manufacturing method
  • Integrated transistor device and corresponding manufacturing method
  • Integrated transistor device and corresponding manufacturing method

Examples

Experimental program
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Embodiment Construction

[0027] 1a)-f) to 10a)-f) show schematic layout diagrams of a method of manufacturing an integrated semiconductor structure according to a first embodiment of the present invention.

[0028] Figures 1a)-f) show a silicon semiconductor substrate 1 in which insulating trenches IT1 and IT2 filled with a dielectric insulating material such as silicon dioxide are formed. The formation of the insulating trenches IT1 , IT2 is performed by means of a silicon nitride mask strip 5 arranged on the upper surface OF of the substrate 1 . After the etching step for forming the insulating trenches IT1 , IT2 , an insulating fill material is deposited and processed by a chemical mechanical polishing step, wherein a silicon nitride mask strip 5 is used as a polishing stop. Therefore, the upper surface of the silicon nitride mask strip 5 and the insulating trenches IT1 , IT2 are at the same level L of height. It should be noted that the thickness of the silicon nitride mask strip 5 is x, where x ...

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PUM

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Abstract

The present invention provides an integrated transistor device comprising: a semiconductor substrate; a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source / drain region formed in an upper region of said pillar; a gate dielectric formed on the bottom of said gate trench and surrounding a lower region of said pillar; a gate formed on said gate dielectric in said gate trench and surrounding a lower region of said pillar; and at least one second source / drain region formed in an upper region of said semiconductor substrate adjoining said gate trench. The present invention also provides a corresponding manufacturing method.

Description

technical field [0001] The invention relates to an integrated transistor device and a corresponding manufacturing method. Background technique [0002] Junction leakage of integrated MOSFET transistors to the substrate is an important issue in device development. For example, in DRAM applications, these parameters have to be optimized for only one contact, such as asymmetric devices. All of these devices for DRAM applications require physical contact. [0003] Recently, asymmetric planar devices, asymmetric three-dimensional devices such as FINCUT and EDU and dual-gate devices have been proposed for DRAM applications. However, they all have a non-gated direct access from the node junction to the substrate. [0004] However, a satisfactory solution that is easily implemented has not been found so far. Contents of the invention [0005] According to a first aspect of the present invention as claimed in claim 1, an integrated transistor device comprises: a semiconductor s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/423H01L27/04H01L27/085H01L21/336H01L21/822H01L21/8232
CPCH01L27/10876H01L29/78H10B12/053H01L29/7827H10B12/395H10B12/0383
Inventor 罗尔夫·韦兹
Owner QIMONDA