Full-chip interconnecting line power consumption optimum layout stage buffer planning method

Abstract

The present invention provides an approaches to planning of chip interconnection line power-optimized layout stage buffer, belonging to interconnection line design optimization field of technology, characterized in containing follow steps: reading module information and interconnection line information, establishing circuit logical topology, initializing side state being 1, calculating time relaxation measurement between the module interconnection lines, calculating each side weighing in the logical topology, obtaining maximal cut set of the logical topological diagram by pre-flowing boost method, distributing time relaxation measurement to each side of the cut set, for each interconnection line, calculating need buffer size and numbers and total interconnection lines power dissipation according to the distribution result of the time relaxation. The invention reduces total power dissipation of the interconnection line without sacrificing circuit time lag performance, having great executing efficiency and industrial application price.

Description

technical field [0001] A buffer planning method for optimal power consumption of a full-chip interconnect line in the layout stage belongs to the field of computer-aided design of integrated circuits, and in particular relates to the field of design optimization of interconnect lines. Background technique [0002] With the continuous shrinking of the integrated circuit process size and the continuous improvement of the integration level, the delay of the interconnection line has greatly affected the performance of the circuit. In order to improve the delay of the interconnect, it is generally necessary to use buffers in the global interconnect. However, these buffers greatly increase power consumption, making interconnect power consumption a significant component of overall chip power consumption. Optimization of interconnect power consumption has become an important consideration in circuit design. [0003] The performance of a circuit depends on the slowest path (the cri...

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Problems solved by technology

Most of the module power optimization models in these algorithms are based on multi-supply voltage technology, and the use of this method has relatively large limitations: on the one hand, multi-supply voltages will bring additional level conversion circuit overhead, and in a given layout In some cases, these algorithms will cause random distribution of low-voltage modules, which greatly increases the design complexity of the power network

Since the relationship between module power consumption and time slack is different from the relationship between interconnect power consumption and time slack, these time slack allocation algorithms for module power optimization cannot be directly transplanted to interconnect power optimization

Therefore, so far, there is no effective method to effectively allocate the amount of time slack to obtain the optimal total power consumption of interconnect lines

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