Full-chip interconnecting line power consumption optimum layout stage buffer planning method

Abstract

The buffer planning method for optimizing the power consumption of the full-chip interconnect line in the layout stage belongs to the field of interconnect line design optimization technology, and is characterized in that it includes the following steps: reading module information and interconnect line information, establishing the logical topology of the circuit, and The state is initialized to 1, the time slack of the interconnection lines between modules is calculated, the weight of each edge in the logical topology graph is calculated, and the maximum cut set of the logical topology graph is obtained by using the pre-flow advancement method, and the time slack is assigned to each edge in the cut set For each segment of interconnection, according to the time slack allocation results, calculate the size and number of buffers required, and the total interconnection power consumed by the circuit. The invention reduces the total power consumption of the interconnection line without affecting the delay performance of the circuit, has high execution efficiency, and has industrial application value.

Description

technical field [0001] A buffer planning method for optimal power consumption of a full-chip interconnect line in the layout stage belongs to the field of computer-aided design of integrated circuits, and in particular relates to the field of design optimization of interconnect lines. Background technique [0002] With the continuous shrinking of the integrated circuit process size and the continuous improvement of the integration level, the delay of the interconnection line has greatly affected the performance of the circuit. In order to improve the delay of the interconnect, it is generally necessary to use buffers in the global interconnect. However, these buffers greatly increase power consumption, making interconnect power consumption a significant component of overall chip power consumption. Optimization of interconnect power consumption has become an important consideration in circuit design. [0003] The performance of a circuit depends on the slowest path (the cri...

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Problems solved by technology

Most of the module power optimization models in these algorithms are based on multi-supply voltage technology, and the use of this method has relatively large limitations: on the one hand, multi-supply voltages will bring additional level conversion circuit overhead, and in a given layout In some cases, these algorithms will cause random distribution of low-voltage modules, which greatly increases the design complexity of the power network

Since the relationship between module power consumption and time slack is different from the relationship between interconnect power consumption and time slack, these time slack allocation algorithms for module power optimization cannot be directly transplanted to interconnect power optimization

Therefore, so far, there is no effective method to effectively allocate the amount of time slack to obtain the optimal total power consumption of interconnect lines

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