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Microprocessor system for controlling or regulating at least partly security-critical processes

A microprocessor, safe technology, applied in the direction of response error generation, redundancy in hardware for data error detection, redundancy code for error detection, etc. design effect

Active Publication Date: 2011-08-31
CONTINENTAL AUTOMOTIVE SYST SHANGHAI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The bus system associated with such a microprocessor system is similarly provided in duplicate, but for cost reasons the memory does not have a completely symmetrical design

Method used

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  • Microprocessor system for controlling or regulating at least partly security-critical processes
  • Microprocessor system for controlling or regulating at least partly security-critical processes
  • Microprocessor system for controlling or regulating at least partly security-critical processes

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Experimental program
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Embodiment Construction

[0038] figure 1 The microcontroller in ® contains two central processing units (CPUs) 1, 2, which operate in a clock-synchronized fashion. Both microcomputers execute the same program. Each unit has its own separate associated address and data bus. The CPU 1 has a full data storage device 7 connected thereto. In addition, the microprocessor system contains a comparator 3 which takes the form of a hardware unit and is used to continuously compare the queued addresses and data on the two bus systems with each other. If there is a mismatch, an error signal is generated. For the purpose of simplifying the illustration, the figures do not show in more detail components that are typically found in a microprocessor system, such as input / output units, read-only memory, etc. These not shown components are essentially based on the redundant core microcontroller described in WO99 / 35543.

[0039] The test data memory 5 on the first bus has a memory capacity which is reduced by a para...

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PUM

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Abstract

The invention relates to a microprocessor system (60) for controlling and / or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second bus system, at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and / or driver components which facilitate data exchange and / or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.

Description

technical field [0001] The invention relates to a microprocessor system and its use in a motor vehicle controller. Background technique [0002] DE 195 29 434 A1 (P 7959) discloses a microprocessor system for safety-critical applications. For reasons of redundancy, such microprocessor systems contain two microprocessor cores of the same type (core redundancy), which execute the same program clock-synchronously and in parallel. The bus system associated with such a microprocessor system is similarly provided in duplicate, but for cost reasons the memory does not have a completely symmetrical design. It has been found that a high false recognition rate can be achieved if one of the two bus systems only stores test data in a test data storage device with a relatively low storage capacity. The test data is unambiguously associated with full data in full memory. Thus, each of the two cores makes all the data available in redundant form, and using the hardware generator, the fu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/10G06F11/16
Inventor W・法伊A・基施鲍姆A・特雷斯科夫
Owner CONTINENTAL AUTOMOTIVE SYST SHANGHAI