AB class buffer circuit
A buffer circuit and current source technology, applied in the direction of logic circuit connection/interface layout, logic circuit coupling/interface using field effect transistors, etc., can solve the problem of input voltage DC voltage difference, filter linearity influence, and voltage tracking characteristics. Good and other problems, to achieve the effect of eliminating the DC voltage difference, good voltage tracking characteristics, and eliminating the substrate effect
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no. 1 example
[0027] Such as figure 2 As shown, the class AB buffer circuit in this embodiment includes 3 PMOS transistors, 3 NMOS transistors, a current source, a class AB output stage and a negative feedback network. Wherein, the source of the PMOS transistor P1 is connected to the power supply VDD, its gate and drain are connected to the input terminal of the current source Ib, and the output terminal of the current source Ib is connected to the ground VSS; the source of the PMOS transistor P2 is connected to the power supply VDD, The gate is connected to the gate of P1, the drain is connected to the drain of NMOS transistor N2; the source of PMOS transistor P2C is connected to the power supply VDD, the gate is connected to the gate of P1, and the drain is connected to the drain of NMOS transistor N2C The gate of the NMOS transistor N2 is connected to the input voltage signal Vin, and the source is connected to the drain of the NMOS transistor N1; the gate of the NMOS transistor N2C is c...
no. 2 example
[0029] and figure 2 The corresponding buffer circuit using a P-type input stage such as image 3 As shown, the class AB buffer circuit in this embodiment includes 3 PMOS transistors, 3 NMOS transistors, a current source, a class AB output stage and a negative feedback network. Wherein, the drain of the PMOS transistor P1 is connected to the sources of the PMOS transistors P2 and P2C, its gate is connected to the bias voltage signal Vc, its source is connected to the power supply VDD and the input terminal of the current source Ib, and the output of the current source Ib The terminal is connected to the drain and gate of the NMOS transistor N1, and the source of N1 is grounded to VSS; the gate of the PMOS transistor P2 is connected to the input voltage signal Vin, and the drain is connected to the drain of the NMOS transistor N2; the gate of the PMOS transistor P2C The drain is connected to the drain of NMOS transistor N2C, the source of N2C is grounded to VSS; the gate of NMO...
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