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Transistor structure and preparation method thereof

A technology of transistor and gate structure, which is applied in the field of transistor structure and can solve problems affecting the performance of transistors

Active Publication Date: 2011-06-22
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Once the source / drain region is in poor contact, it will seriously affect the performance of the transistor operation

Method used

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  • Transistor structure and preparation method thereof
  • Transistor structure and preparation method thereof
  • Transistor structure and preparation method thereof

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Experimental program
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Embodiment Construction

[0036] The present invention relates to a transistor structure that maintains sufficient source / drain contact region width and area within a relatively small cell size. The transistor structure can ensure the electrical connection of the source / drain and the operation performance of the transistor under the condition of making good use of the chip space, thereby improving the competitiveness.

[0037] see figure 1 , which depicts a preferred embodiment of the transistor structure of the present invention. The transistor structure 100 of the present invention includes a substrate 110 , a gate trench 120 , a gate structure 130 , a source doped region 140 , a drain doped region 150 , and a gate channel 160 . The transistor structure 100 is covered with a dielectric layer 170 . The substrate 110 suitable for the transistor structure 100 of the present invention may be a semiconductor substrate having a crystal lattice orientation, such as a silicon or germanium substrate.

[00...

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Abstract

The invention discloses a transistor structure and a method for preparing the structure. The transistor structure comprises a grid electrode groove which is positioned in a substrate material and comprises a pen type bottom whose width is larger than the neck portion of the pen type bottom, the neck portion comprises a first conducting layer, and the pen type bottom comprises a second conducting layer, a grid electrode structure which is positioned on the grid electrode groove and is electrically connected with the first conducting layer, a source electrode doping area and a drain doping area which are respectively positioned on one side of the grid electrode groove, and a grid electrode channel which is arranged between the drain doping area and the source electrode doping area. The pen type bottom is provided with a vertical sidewall and a V-shaped tip, and the vertical sidewall and the V-shaped tip are formed along a lattice direction of the substrate.

Description

technical field [0001] The invention relates to a transistor structure, in particular to a transistor structure with a wider bottom in a gate trench. Background technique [0002] A transistor structure composed of a source, a gate and a drain is widely used in electronic products. Wherein, the source / drain doped regions located on both sides of the gate are electrically connected to the outside through the source / drain contact regions respectively. [0003] With the trend of shrinking critical dimensions, the space for forming source / drain contact regions is also greatly reduced. Taking a transistor structure with a line width of 40nm as an example, the width of the source / drain contact region used to form the source / drain contact region in the traditional process is only about 30nm. Considering the photolithography error and alignment error in actual operation, it is very difficult to accurately form the source / drain contact region with a width of about 30 nm. Once the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/423H01L21/336H01L21/28
Inventor 李培瑛林瑄智
Owner NAN YA TECH