Data processing apparatus with shadow register and method thereof

A data processing device and data processing technology, applied in the direction of electrical digital data processing, register devices, machine execution devices, etc.

Inactive Publication Date: 2011-09-21
HIMAX TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a data processing device and its method, which can effectively solve the problem that traditional data processing devices must use four registers to perform multiply-accumulate (MLA) operations, and can use fewer registers to perform Advantages of Performing MLA Operations

Method used

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  • Data processing apparatus with shadow register and method thereof
  • Data processing apparatus with shadow register and method thereof
  • Data processing apparatus with shadow register and method thereof

Examples

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no. 1 example

[0029] Please refer to figure 2 , which is a block diagram of a data processing device according to a first embodiment of the present invention. The data processing device 10 includes a register bank (Register Bank) 12 , a shadow register (ShadowRegister) 14 and an operation unit 16 . The register group 12 includes a plurality of registers, and these registers are respectively used to store a plurality of operands. The shadow register 14 is used for backing up the first operand among the operands in response to the first control signal, and storing the first backed up operand. The first operand is stored in a first of these registers. The arithmetic operation unit 16 is used for performing at least one arithmetic operation on the operands in the registers in response to the arithmetic operation instruction to obtain the operational data Qd, and store the operational data Qd in the first register. Next, a case where the data processing device 10 is a multiply-accumulate (ML...

no. 2 example

[0036] Please refer to Figure 4 , which is a block diagram of a data processing device according to a second embodiment of the present invention. The difference between the data processing device 10' of this embodiment and the data processing device in the first embodiment is that the data processing device 10' further includes a logic unit 18 to generate operands Qa', Qb according to operands Qa, Qb and Qc ' and Qc'. In addition, the calculation operation unit 16' in the data processing device 10' performs the calculation: Qd'=Qa'×Qb'+Qc', and outputs the calculation data Qd'.

[0037] The logic unit 18 is further used for receiving operation data Qd', selection signals SS1-SS3 and control signal SC2. The logic unit 18 is used to select one of the operands Qa, Qb, and Qc as the operand Qa' in response to the selection signal SS1, and select the other of the operands Qa, Qb, and Qc as the operand in response to the selection signal SS2. Qb' selects yet another one of the o...

no. 3 example

[0042] Please refer to Figure 5 , which shows a block diagram of a data processing device that fails at the third stage according to the present invention. The difference between the data processing device 20 of the third embodiment and the data processing device 10' of the second embodiment is that the register set 12' additionally includes registers R4 to Rm, wherein m is a natural number greater than 3. Another difference is that the logic unit 18' of the third embodiment transmits the operation data Qd' to one of the registers R4 to Rm when the data processing device 20 intends to perform an operation that needs to refer to the operand Qc.

[0043] For example, the logic unit 18' transmits the operation data Qd' previously stored in the register R3 to the register R4 before transmitting the backup operand Qr1' stored in the shadow register 14' to the register R3. As mentioned above, backup operand Qr1' is substantially equal to the operand previously stored in register R...

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Abstract

A data processing apparatus comprising a register bank, a shadow register and an arithmetic operation unit is provided. The register bank comprises a number of registers for respectively storing a number of operands, respectively. The registers comprise a first register, a second register and a third register, and the operands include a first operand, a second operand and a third operand, wherein the registers are n-bit registers, and n is a nature number, the first operand is stored in a first register, the second operand is stored in the second register, and the third operand is stored in the third register. The shadow register is for storing first backup operand for making a backup of a first operand, which is stored in a first register among the registers in response to first control signal. The arithmetic operation unit is for multiplying the third and the second operand and adding a product of the third and the second operand and the first operand to obtain an operational data, and storing the operational data in the first register in response to an arithmetic operation command after the backup of the first operand.

Description

technical field [0001] The present invention relates to a data processing device and method, and in particular to a data processing device and method capable of reducing the number of registers required for executing a multiply-accumulate (MLA) instruction. Background technique [0002] With the rapid development of technology, the data processing device is, for example, a microprocessor capable of performing Multiply-accumulate (MLA) operations. It has been widely used in many different applications. [0003] Please refer to figure 1 , which shows a block diagram of a conventional data processing device. In the traditional microprocessor 100, the registers Re1-Re4 in the register bank (Register Bank) 120 are used to store data Pa, Pb, Pc and operation data Pd respectively. Wherein, the operation data Pd satisfies the equation: Pd=Pa×Pb+Pc [0004] However, a conventional data processing device must use four registers Re1˜Re4 to perform MLA operations. Therefore, how to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/302
CPCG06F9/30116G06F9/3001G06F9/3863G06F9/3012G06F9/30105
Inventor 陈俊裕刘恕民
Owner HIMAX TECH LTD
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