Star-cluster double-loop on chip network topology construction

Abstract

The present invention provides a network topology structure on a star-cluster double-loop (SCDL), and the structure consists of 4m*2k processing units and 4m switching nodes, wherein, each 2k processing units are connected to form a star network topology structure, therefore, 4m star structures are formed; switching nodes of the 4m star structures are connected to form DL (2m) interconnection network topology structures. The present invention has the characteristics of canonicity, symmetry, planarity, excellent extendibility, lower network cost, simple switching nodes and simple routing policy. According to the present invention, a switching node is connected with four processing units, therefore, communication distance between processing units is reduced, localization feature of the system is improved, delay of the system is reduced and throughput of the system is improved. A novel Johnson coding method can be adopted by the switching nodes and processing units of the present invention, and the method make the coding of the switching nodes and processing units imply information of adjacent nodes and links of the interconnection network; therefore, the route algorithm design is simple.

Description

technical field [0001] The invention belongs to the technical field of on-chip networks, in particular to a network topology structure for on-chip networks, which is called a star-cluster dual-ring on-chip network topology structure. Background technique [0002] With the continuous development of semiconductor technology, the current SoC can include one or more processors, memories, analog circuits, digital-analog hybrid circuits, and on-chip programmable logic (Intellectual Properties) IP cores. However, as the number of IP cores included in SoC increases, the existing SoC technology based on bus structure is facing huge challenges in terms of performance, power consumption, delay and reliability. In order to overcome various problems faced by complex SoCs, some research institutions have borrowed and absorbed some ideas of parallel computing, and proposed an integration method of IP cores of complex SoCs with communication as the core, that is, Network-on-Chip (NoC). ). ...

AI Technical Summary

Problems solved by technology

Currently, it is not theoretically possible to prove that an optimal topology can be used for any given application

Although a dedicated network structure can improve performance, reduce power consumption, and reduce area, using an irregular grid topology will cause design problems such as layout design and uneven line lengths.

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