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Conditional execute bit in a graphics processor unit pipeline

A graphics processor, conditional execution technology, applied in the field of filing

Active Publication Date: 2012-09-19
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, portable or handheld devices often have limitations relative to larger devices such as desktop computers
For example, since portable devices are often battery powered, power consumption is a concern
Also, due to their small size, the available space inside portable devices is limited

Method used

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  • Conditional execute bit in a graphics processor unit pipeline
  • Conditional execute bit in a graphics processor unit pipeline
  • Conditional execute bit in a graphics processor unit pipeline

Examples

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Embodiment Construction

[0025] Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the embodiments of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, one skilled in the art will recognize that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodime...

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Abstract

The invention relates to a conditional execute bit in a graphics processor unit pipeline. An arithmetic logic stage in a graphics processor unit includes a number of arithmetic logic units (ALUs). An instruction is applied to sets of operands comprising pixel data associated with different pixels. The value of a conditional execute bit determines how the pixel data in a set of operands is processed by the ALUs.

Description

[0001] Related U.S. Applications [0002] This application is related to U.S. Patent Application Serial No. 11 / 893,499, filed August 15, 2007, by T. Bergland et al., entitled "Buffered Deserialization in a Graphics Processor Unit Pipeline Buffering Deserialized Pixel Data in a Graphics Processor Unit Pipeline" with Attorney Docket No. NVID-P003219, assigned to the assignee of the present invention, and incorporated herein by reference in its entirety middle. [0003] This application is related to U.S. Patent Application Serial No. 11 / 893,622, filed August 15, 2007, by T. Bergland et al., entitled "Shared Readable and Writable Global Values" (Shared Readable and Writeable Global Values ​​in a Graphics Processor Unit Pipeline), with Attorney Docket No. NVID-P003476, assigned to the assignee of the present invention, and incorporated herein in its entirety by Incorporated herein by reference. [0004] technical field [0005] Embodiments of the invention relate generally to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T1/20G06F9/38G06F7/57G06T15/00
CPCG06T15/005G06F9/06G06F9/30
Inventor 泰森·J·伯兰格克雷格·M·奥克鲁丽卡
Owner NVIDIA CORP