System and method for filtering 3G data packet based on FPGA
A filtering system and data packet technology, applied in the field of TD-SCDMA network security, can solve the problems of lagging software processing speed and not considering hardware characteristics, etc., and achieve the effect of increasing the number of users and wide application prospects
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[0030] For chip selection, we use Virtex-5 LX50T Field Programmable Gate Array from Xilinx Company, whose main hardware parameters are as follows:
[0031] The array in the configurable logic block (CLB) is: 120×30; the slice is: 7200, and each slice contains four LUTs and four flip-flops; the maximum distributed RAM is: 480Kb;
[0032] Block RAM module up to 2160Kb
[0033] Number of Ethernet MAC modules: 4
[0034] Number of RocketIO GTP transceivers: 12, operating speed is 100Mb / s~3.2Gb / s, full-duplex serial transceiver
[0035] Total number of I / O groups: 15
[0036] Maximum number of user I / Os: 480
[0037] Below in conjunction with accompanying drawing, the technical scheme of invention is described in detail:
[0038] Such as figure 1 As shown, the position of the present invention in the supervision system as a whole can be seen, the filter equipment is connected in series between SGSN and GGSN, to ensure that the data link between SGSN and GGSN is unobstructed, t...
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