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Method for making shallow groove

A shallow trench and patterning technology, which is applied in the fields of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of device electrical performance or reliability impact, and the lack of apex corners in shallow trench isolation regions, etc. Effects of corner defects, elimination of missing corners, and reduction of etching variance

Inactive Publication Date: 2011-07-20
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, actual production finds that, as Figure 4 As shown, after the formation of the shallow trench 40, there is a sharp defect 42 at the top of the side wall of the shallow trench 40, and the existence of the sharp defect 42 makes it possible to form After the pad oxide layer, the thickness of the pad oxide layer covering the sharp corners is smaller than the thickness of the pad oxide layer at other positions, so that when the cleaning operation performed after the above-mentioned planarization is performed, the sharp corners are covered. The pad oxide layer at the position is easier to be removed, and exposes the sharp corner, so that the sharp corner is easy to be oxidized and removed during the cleaning process, or oxidized during the time interval with the subsequent operation, Then it is removed in the subsequent cleaning process, resulting in missing top corners of shallow trench isolation regions
The absence of the top corner of the shallow trench isolation region may have a potential impact on the electrical performance or reliability of the device containing the shallow trench

Method used

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Embodiment Construction

[0019] Although the invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it should be understood that those skilled in the art can modify the invention described herein and still achieve the advantageous effects of the invention. Therefore, the following description should be understood as a broad instruction for those skilled in the art, rather than as a limitation of the present invention.

[0020] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with sy...

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Abstract

A method for making a shallow groove comprises the steps: a passivating layer and a patterned etching resistant layer are formed on a semiconductor substrate; the patterned etching resistant layer is used as a covering film, and partial thickness of the passivating layer is removed by first etching gas; the passivating layer etched is used as a hard covering film, the rest passivating layer and partial thickness of the semiconductor substrate are etched by second etching gas which is different from the first etching gas, and the shallow groove is formed. The method can reduce and even eliminate the tip angle on the top end of the side walls of the groove, and then reduce and even eliminate the apex angle deletion in the isolation zone of the shallow groove.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a shallow trench. Background technique [0002] In the traditional process, the steps of forming shallow trenches include, step 11: as figure 1 As shown, a passivation layer 20 and a patterned resist layer 30 are formed on the semiconductor substrate 10; step 12: as figure 2 As shown, using the patterned resist layer 30 as a mask, etch the passivation layer 20 to form the etched passivation layer 22; step 13: as image 3 As shown, using the etched passivation layer 22 as a hard mask, part of the semiconductor substrate 10 is etched to form the shallow trench 40 . Then, using the passivation layer as a stop layer, filling and planarizing the shallow trench; removing the passivation layer to form a shallow trench isolation region. The semiconductor substrate is a semiconductor substrate that has defined device active regions and needs to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311H01L21/308H01L21/76
Inventor 赵林林
Owner SEMICON MFG INT (SHANGHAI) CORP
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