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Floating-point multiply-add fused unit compatible with double-precision and double-single-precision and compatibility processing method thereof

A processing method and single-precision technology, which can be used in electrical digital data processing, digital data processing components, instruments, etc., and can solve the problems of adding floating-point multiplier-adders and increasing area overhead floating-point multiplier-adders.

Active Publication Date: 2011-11-16
LOONGSON TECH CORP
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Problems solved by technology

In the prior art, either a large amount of area overhead is added to reduce the delay of the floating-point multiply-accumulator, or the delay of the floating-point multiply-accumulator is increased in order to improve single-precision performance and support double-single-precision operations

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  • Floating-point multiply-add fused unit compatible with double-precision and double-single-precision and compatibility processing method thereof
  • Floating-point multiply-add fused unit compatible with double-precision and double-single-precision and compatibility processing method thereof
  • Floating-point multiply-add fused unit compatible with double-precision and double-single-precision and compatibility processing method thereof

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Embodiment Construction

[0048] In order to make the object, technical solution and advantages of the present invention clearer, the floating-point multiply-accumulator and its floating-point multiply-accumulate processing method of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention rather than limit the present invention.

[0049] In order to reduce the delay of the floating-point multiplier-adder, the floating-point multiplier-accumulator in the embodiment of the present invention adopts a dual-path algorithm, and on the basis of the dual-path algorithm, double-precision and double-single-precision operations are performed on the two paths for multiplexing.

[0050] The two-path algorithm is to calculate the exponent difference d1=exp(A)-(exp(B)+exp(C) according to the exponent of the data operand A, the exponen...

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Abstract

The invention discloses a floating-point multiply-add fused unit compatible with double-precision and double-single-precision and a compatibility processing method thereof. The floating-point multiply-add fused unit comprises a multiplication tree, a shifter, an LZA, an LOD and an adder, which can respectively carry out both the operation of two single-precision and the operation of a double-precision. Two sections are formed as much as possible or the input data is compatibly processed so as to achieve the purpose of parallel processing of double-precision and single-precision. The techniqueensures the compatible operation of double-precision and single-precision under the conditions of minimizing or minimally increasing the areas of the floating-point multiply-add fused components, thereby improving the performance of the single-precision operation of the floating-point multiply-add fused unit under the condition of lesser area overhead.

Description

technical field [0001] The invention relates to the technical field of microprocessor processing, in particular to a single-precision and double-single-precision floating-point multiply-adder and a floating-point multiply-add compatible calculation processing method thereof. Background technique [0002] In existing microprocessors, in order to improve the efficiency of floating-point calculations, floating-point multiply-adders (Multiply-Add Fused) are usually used to implement continuous floating-point multiplication and addition operations (expressed as A×B+C). Compared with separate floating-point multipliers and adders, the use of floating-point multiply-accumulators not only reduces the delay of continuous execution of multiplication and addition, but also reduces hardware overhead, while improving the accuracy of multiply-add operations. This is because if a multiplier and an adder are used to implement the multiplication and addition operation, a rounding and normali...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/57
Inventor 郭崎齐子初胡伟武
Owner LOONGSON TECH CORP
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