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Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit

An integrated circuit and potential technology, applied in the direction of logic circuit connection/interface layout, logic circuit coupling/interface using field effect transistors, etc., can solve the problems of large power consumption, large current, and increased potential pull-up circuit area, etc., to achieve The effect of strong anti-noise interference ability

Active Publication Date: 2012-11-28
NINGBO SEMICON INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the existing potential pull-up circuit, when the I / O port inputs a low level, a current will be formed between the power supply VCC and the I / O port through the potential pull-up circuit, resulting in power consumption. To reduce power consumption It is necessary to increase the resistance or increase the gate length of the NMOS transistor, but this will greatly increase the area of ​​the potential pull-up circuit, and there are more serious contradictions: if the drive capability of the I / O port is required to be strong, and the response frequency High, the impedance of the potential pull-up circuit will be small. In this case, if the I / O port inputs a low level, the current generated from the power supply VCC to the I / O port through the potential pull-up circuit will be large, and the power consumption will inevitably be great
The existing potential pull-down circuit also has the same disadvantages as the potential pull-up circuit. Obviously, the existing potential pull-up and pull-down circuits are not suitable for use in low-power, high-integration integrated circuits

Method used

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  • Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit
  • Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit
  • Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0020] Embodiment 1: a potential pull-up circuit of the I / O port of an integrated circuit, such as figure 2 As shown, it includes a first delay switch control module delay1, a first PMOS transistor P1, a second PMOS transistor P2, a first inverter U1, a second inverter U2, a first resistor R1 and a second resistor R2, The first terminal of the first resistor R1 is the input terminal IN1 of the entire potential pull-up circuit, and the second terminal of the first resistor R1 is respectively connected to the input terminal of the first inverter U1 and the first terminal of the second resistor R2, The second end of the second resistor R2 is respectively connected to the drain of the first PMOS transistor P1 and the drain of the second PMOS transistor P2, and the gate of the second PMOS transistor P2 is connected to the first delay switch control module delay1, The source of the second PMOS transistor P2, the substrate of the second PMOS transistor P2, the source of the first PM...

Embodiment 2

[0027] Embodiment two: a potential pull-down circuit of the I / O port of an integrated circuit, such as image 3 As shown, it includes a second delay switch control module delay2, a first NMOS transistor N1, a second NMOS transistor N2, a third inverter U3, a fourth inverter U4, a third resistor R3 and a fourth resistor R4, The first terminal of the third resistor R3 is the input terminal IN2 of the entire potential pull-down circuit, the second terminal of the third resistor R3 is respectively connected to the input terminal of the third inverter U3 and the first terminal of the fourth resistor R4, the second The second ends of the four resistors R4 are respectively connected to the drain of the first NMOS transistor N1 and the drain of the second NMOS transistor N2, the gate of the first NMOS transistor N1 is connected to the second delay switch control module delay2, the second The source of an NMOS transistor N1, the substrate of the first NMOS transistor N1, the source of ...

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Abstract

The invention discloses a potential pull-up circuit and a pull-down circuit of an I / O port of an integrated circuit. The potential pull-up circuit outputs high level when no signal is input, thus realizing level pull-up function of the I / O port and having strong noise interference resistance; whether signals are input or not, zero static power consumption can be realized; the driving capability and frequency characteristic of the flexibly-regulated I / O port can be realized by regulating the current capability of a first inverter and a second inverter which are the driving stage of the whole circuit; the potential pull-down circuit outputs low level when no signal is input, thus realizing the pull-down function of the I / O port and having strong noise interference resistance; whether signals are input or not, zero static power consumption is realized; and the driving capability and frequency characteristic of the flexibly-regulated I / O port can be realized by regulating the current capability of a third inverter and a fourth inverter which are the driving stage of the whole circuit.

Description

technical field [0001] The invention relates to a potential pull-up and pull-down circuit, in particular to a potential pull-up circuit and pull-down circuit of an I / O port of an integrated circuit. Background technique [0002] The I / O ports of many integrated circuits need to set a default level, and keep the pull-up or pull-down of the potential when there is no signal input. A simple application of the existing potential pull-up is formed by connecting a fixed resistor to the power supply VCC at the I / O port, and a simple application of the potential pull-down is to connect a fixed resistor to the ground GND at the I / O port In this potential pull-up and pull-down circuit, MOS transistors can also be used instead of fixed resistors, such as Figure 1a The potential pull-up circuit shown and Figure 1b Potential pull-down circuit shown. Figure 1a The shown potential pull-up circuit includes an NMOS transistor N, the drain and the gate of the NMOS transistor N are connect...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0185
Inventor 王贤吉曾强
Owner NINGBO SEMICON INT CORP
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