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pull-up resistor circuit

A resistance circuit and voltage technology, applied in the direction of logic circuit connection/interface layout, etc., to achieve the effect of eliminating backflow current and improving reliability

Active Publication Date: 2018-04-27
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, in the high-voltage tolerance mode, that is, when the voltage on the output terminal OUT is higher than the voltage on the power supply terminal VDD (for example, the power supply voltage is usually 3.3V, and the voltage on the bus is 5V, when the When the output terminal OUT is connected to the bus), even if the control signal RE is a high-level signal, since the voltage of the high-level signal will not be higher than the power supply voltage, the PMOS transistor MP0 will still be turned on. resulting in a sink current flowing from the output terminal OUT to the power supply terminal VDD

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0061] image 3 is a circuit diagram of the pull-up resistor circuit of this embodiment. refer to image 3 , the pull-up resistor circuit includes a power supply terminal VDD, an output terminal OUT, a first PMOS transistor MP1 and a transmission unit. The transmission unit includes a second PMOS transistor MP2 , a third PMOS transistor MP3 and a control signal generation unit, and the control signal generation unit includes a first switch unit 31 and a second switch unit 32 . The power supply terminal VDD, the output terminal OUT, the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected with figure 2 Similar and will not be repeated here.

[0062] In this embodiment, the first switch unit 31 includes a fourth PMOS transistor MP4, the second switch unit 32 includes a fifth PMOS transistor MP5 and a first NMOS transistor MN1, and when the first switch unit 31 is turned on The impedance is smaller than the impedance when ...

Embodiment 2

[0074] Figure 4 is a circuit diagram of the pull-up resistor circuit of this embodiment. refer to Figure 4 , the pull-up resistor circuit includes a power supply terminal VDD, an output terminal OUT, a first PMOS transistor MP1 and a transmission unit, and the transmission unit includes a second PMOS transistor MP2, a third PMOS transistor MP3 and a control signal generating unit.

[0075] The power supply terminal VDD, the output terminal OUT, the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected with figure 2 Similar and will not be repeated here. The control signal generation unit includes a first switch unit 41 and a second switch unit 42 , the first switch unit 41 includes a fourth PMOS transistor MP4 , and the fourth PMOS transistor MP4 can refer to the description in Embodiment 1.

[0076] The second switch unit 42 includes a second NMOS transistor MN2 and a third NMOS transistor MN3.

[0077] Specifically, ...

Embodiment 3

[0084] The pull-up resistor circuit of this embodiment includes a power supply terminal, an output terminal, a first PMOS transistor and a transmission unit, and also includes a bias voltage generation circuit suitable for generating a bias voltage Vbias. The power supply terminal, output terminal, first PMOS transistor and transmission unit are similar to those in Embodiment 1 and Embodiment 2, and will not be repeated here.

[0085] Figure 5 is a circuit diagram of the bias voltage generation circuit of this embodiment. refer to Figure 5 , the bias voltage generation circuit includes a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7.

[0086] Specifically, the gate of the sixth PMOS transistor MP6 is connected to the drain of the seventh PMOS transistor MP7 and the output terminal OUT, and the source of the sixth PMOS transistor MP6 is connected to the power supply terminal VDD and the seventh PMOS transistor MP7. The gate of MP7, the drain of the sixth PMOS...

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Abstract

A pull-up resistor circuit includes a power supply terminal, an output terminal, a first PMOS transistor and a transmission unit; the source of the first PMOS transistor is connected to the power supply terminal, and the drain of the first PMOS transistor is connected to the output terminal, the substrate of the first PMOS transistor is suitable for inputting a bias voltage, and the voltage value of the bias voltage is equal to the voltage value of the larger voltage among the voltage of the power supply terminal and the voltage of the output terminal; the transmission The unit is adapted to transmit a pull-up control signal to the gate of the first PMOS transistor when the voltage of the power supply terminal is greater than or equal to the voltage of the output terminal, and to transmit the pull-up control signal to the gate of the first PMOS transistor when the voltage of the power supply terminal is less than the voltage of the output terminal. The voltage of the output terminal is transmitted to the gate of the first PMOS transistor. When the pull-up resistor circuit provided by the technical solution of the present invention operates in the high-voltage tolerance mode, no backflow current is generated, which improves the reliability of the entire integrated circuit.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a pull-up resistor circuit. Background technique [0002] Pull-up resistor circuits are widely used in integrated circuits, especially in I / O circuits. Many I / O ports usually need to be set to a default high level. In some cases where there is no signal input, the I / O port is pulled up to a high level through a pull-up resistor circuit. [0003] figure 1 It is an existing pull-up resistor circuit. refer to figure 1 , the pull-up resistor circuit includes a power supply terminal VDD, an output terminal OUT and a PMOS transistor MP0. The source and substrate of the PMOS transistor MP0 are connected to the power supply terminal VDD, the drain of the PMOS transistor MP0 is connected to the output terminal OUT, and the gate of the PMOS transistor MP0 is suitable for inputting a control signal RE. The power supply terminal VDD is suitable for receiving a power supply v...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0175
Inventor 朱恺陈捷翁文君莫善岳
Owner SEMICON MFG INT (SHANGHAI) CORP
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