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Pull-up resistor circuit

A resistance circuit, voltage technology, applied in the direction of logic circuit, logic circuit connection/interface layout, electrical components, etc., to eliminate backflow current and improve reliability

Active Publication Date: 2015-05-27
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, in the high voltage tolerance mode, that is, when the voltage on the output terminal OUT is greater than the voltage on the power supply terminal VDD (for example, the power supply voltage is usually 3.3V, and the voltage on the bus is 5V, when the When the output terminal OUT is connected to the bus), even if the control signal RE is a high-level signal, since the voltage of the high-level signal will not be greater than the power supply voltage, the PMOS transistor MP0 will still be turned on, resulting in The sink current flowing from the output terminal OUT to the power supply terminal VDD

Method used

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Examples

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Comparison scheme
Effect test

Embodiment 1

[0055] image 3 is a circuit diagram of the pull-up resistor circuit of this embodiment. refer to image 3 , the pull-up resistor circuit includes a power supply terminal VDD, an output terminal OUT, a first PMOS transistor MP1, a second PMOS transistor MP2 and a control signal generating unit.

[0056] The power supply terminal VDD, the output terminal OUT, the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected with figure 2 Similar and will not be repeated here. The control signal generation unit includes a first switch unit 31 and a second switch unit 32 .

[0057] In this embodiment, the first switch unit 31 includes a third PMOS transistor MP3, the second switch unit 32 includes a fourth PMOS transistor MP4 and a first NMOS transistor MN1, and when the first switch unit 31 is turned on The impedance is smaller than the impedance when the second switch unit 32 is turned on. Therefore, when the first switch unit 31 and the second switch unit 32...

Embodiment 2

[0074] Figure 4 is a circuit diagram of the pull-up resistor circuit of this embodiment. refer to Figure 4 , the pull-up resistor circuit includes a power supply terminal VDD, an output terminal OUT, a first PMOS transistor MP1, a second PMOS transistor MP2 and a control signal generating unit.

[0075] The power supply terminal VDD, the output terminal OUT, the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected with figure 2 Similar and will not be repeated here. The control signal generation unit includes a first switch unit 41 and a second switch unit 42 , the impedance of the first switch unit 41 is smaller than the impedance of the second switch unit 42 when it is turned on. The first switch unit 41 includes a third PMOS transistor MP3, and for the third PMOS transistor MP3, reference may be made to the description in Embodiment 1.

[0076] The second switch unit 42 includes a second NMOS transistor MN2 and a third NMOS transistor MN3.

[0...

Embodiment 3

[0086] The pull-up resistor circuit of this embodiment includes a power supply terminal, an output terminal, a first PMOS transistor, a second PMOS transistor, and a control signal generating unit, and also includes a bias voltage generating circuit suitable for generating a bias voltage Vbias. The power supply terminal, output terminal, first PMOS transistor, second PMOS transistor and control signal generation unit are similar to those in Embodiment 1 and Embodiment 2, and will not be repeated here.

[0087] Figure 5 is a circuit diagram of the bias voltage generation circuit of this embodiment. refer to Figure 5 , the bias voltage generating circuit includes a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6.

[0088] Specifically, the gate of the fifth PMOS transistor MP5 is connected to the drain of the sixth PMOS transistor MP6 and the output terminal OUT, and the source of the fifth PMOS transistor MP5 is connected to the power supply terminal VDD and the s...

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Abstract

A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input / output (I / O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a pull-up resistor circuit. Background technique [0002] Pull-up resistor circuits are widely used in integrated circuits, especially in I / O circuits. Many I / O ports usually need to be set to a default high level. In some cases where there is no signal input, the I / O port is pulled up to a high level through a pull-up resistor circuit. [0003] figure 1 It is an existing pull-up resistor circuit. refer to figure 1 , the pull-up resistor circuit includes a power supply terminal VDD, an output terminal OUT and a PMOS transistor MP0. The source and substrate of the PMOS transistor MP0 are connected to the power supply terminal VDD, the drain of the PMOS transistor MP0 is connected to the output terminal OUT, and the gate of the PMOS transistor MP0 is suitable for inputting a control signal RE. The power supply terminal VDD is suitable for receiving a power supply v...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/0185
CPCH03K19/00315H03K19/018507
Inventor 朱恺陈捷翁文君莫善岳郭之光
Owner SEMICON MFG INT (SHANGHAI) CORP
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