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Memory power gating circuit and method

A technology of power gating and power voltage, applied in static memory, read-only memory, information storage, etc., can solve problems such as power dissipation or static power dissipation increase, chip failure, shortening battery life of mobile systems, etc.

Active Publication Date: 2015-11-25
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The increased power dissipation causes several problems including shortened battery life in mobile systems, expensive packaging and cooling schemes, and can also lead to chip failure
Among the various factors that cause power dissipation, power dissipation caused by leakage or static power dissipation is increasing and is expected to exceed dynamic power dissipation in the near future

Method used

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  • Memory power gating circuit and method
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  • Memory power gating circuit and method

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Embodiment Construction

[0019] During the data retention mode of the memory array, the transistors of the header function as diodes. The diode currents of the transistors are small, so a large number of transistors in the header are used to provide the diode currents needed to hold the data information of the memory. However, a large number of transistors requires a large area, which increases the size of the memory. Conventional power gating circuits are known to be vulnerable to process-voltage-temperature (PVT) variations.

[0020] Active biasing methods have been proposed to reduce the power dissipation of memories. Active biasing uses an operational amplifier to continuously monitor and adjust the voltage level of the memory. However, operational amplifiers require a large amount of memory area and are not compatible with embedded memories such as embedded SRAM.

[0021] It should be understood that the following disclosure provides many different embodiments or examples for implementing diff...

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Abstract

This invention provides a power selective circuit of memory device configured to link the memory array with internal volatage, where said power selective circuit includes a signal output circuit which increases the internal voltage of memory array under the condition of the internal voltage is lower than the first threhold voltage and decreases the internal voltage of memory array under the condition of the internal voltage is higher than the second threhold voltage so as to keep the internal voltage between the first threhold voltage and the second threhold voltage. Furthermore, a method for storing the data of memory array of this invention is provided.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Application Serial No. 61 / 154,744, filed February 23, 2009, which application is hereby incorporated by reference. technical field [0003] The present invention relates generally to the field of semiconductor devices, and more particularly, to apparatus and methods for controlling the power requirements of memory. Background technique [0004] The semiconductor integrated circuit (IC) industry has experienced rapid development. Technological advances in IC materials and design have produced generations of ICs, each generation having smaller and more complex circuits than the previous generation. Scaling of IC technology to the nanometer state has increased power dissipation. The increased power dissipation causes several problems, including shortened battery life in mobile systems, expensive packaging and cooling schemes, and can also cause chip failures. Among various factors...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06G11C16/02
Inventor 詹伟闵刘逸群周绍禹
Owner TAIWAN SEMICON MFG CO LTD