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Reading and writing operation method and equipment of FPGA (Field Programmable Gate Array) equipment in DDR (Double Data Rate) interface

A technology for writing operations and devices, applied in the field of communications, which can solve the problems of single DDR system structure and inability to meet system diversity.

Active Publication Date: 2013-06-05
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The existing DDR system composed of DDR controller and DDR memory has a single structure and cannot meet the requirements of system diversity

Method used

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  • Reading and writing operation method and equipment of FPGA (Field Programmable Gate Array) equipment in DDR (Double Data Rate) interface
  • Reading and writing operation method and equipment of FPGA (Field Programmable Gate Array) equipment in DDR (Double Data Rate) interface
  • Reading and writing operation method and equipment of FPGA (Field Programmable Gate Array) equipment in DDR (Double Data Rate) interface

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Experimental program
Comparison scheme
Effect test

Embodiment 4

[0098] The FPGA device in Embodiment 4 may further include a data processing module 36 for processing data stored in the FPGA; or, processing data received from devices other than the FPGA. The data output by the data output module 34 may be data obtained and processed by the data processing module 36 from other devices other than the DDR controller. Therefore, the FPGA device in Embodiment 4 can unidirectionally transmit data to the DDR controller. It is also possible to write the data sent by the DDR controller into the RAM of the FPGA. After the data processing module inside the FPGA processes the written data, it is then read out by the DDR controller to realize bidirectional data exchange between the DDR controller and the FPGA device. transmission.

[0099] Take the second PLL module 32 to adjust the phase of the clock signal as an example below, as shown in Figure 4 (b), the second PLL module 32 can include an input port 41, an adjustment component 42 and an output port...

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Abstract

The invention discloses a writing operation method of FPGA (Field Programmable Gate Array) equipment in a DDR (Double Data Rate) interface. The method comprises the following steps of: receiving clock signals of an information sending port of a DDR controller by FPGA equipment; receiving a writing operation command from the DDR controller, and converting an external input address from the DDR controller into an internal memory address of the FPGA equipment according to the clock signals of the information sending port of the DDR controller; adjusting the phase of DQ and DQS carrying external input data sent by the DDR controller, wherein the difference of phases of the DQS signal and DQ signal after the adjustment is 1 / 4 period; and sampling data from the DQ signal and the DQS signal according to the clock signals of the information sending port of the DDR controller to obtain external input data, and storing according to the internal memory address. The invention also provides a novel DDR system, a reading operation method of the FPGA equipment and the FPGA equipment.

Description

technical field [0001] The invention relates to the communication field, in particular to a field programmable gate array read and write operation method applied in a DDR interface and a field programmable gate array device. Background technique [0002] A Double Data Rate (DDR) system usually includes a DDR controller (DDR controller) and a DDR memory (DDR memory). The DDR controller sends initialization, read, For commands such as write operations, the DDR memory correctly responds to the received command according to the definition of the DDR specification, and receives or sends the data commanded by the DDR controller. [0003] The existing DDR system composed of DDR controller and DDR memory has a single structure, which cannot meet the requirements of system diversity. Contents of the invention [0004] Embodiments of the present invention provide an FPGA read and write operation method in a DDR interface and an FPGA device, and propose a new DDR system composed of ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/10
Inventor 和宏海王红霞刘雁行陈威
Owner ZTE CORP
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