Out-of-order execution microprocessor and operating method therefor

Abstract

An out-of-order execution microprocessor for reducing load instruction replay likelihood due to store collisions includes: a first queue memory including a plurality of items; a second queue memory including a plurality of items; and a buffer alternative name list which is coupled on first and second queue memories for generating a plurality of dependency according to a plurality of instructions which are arranged according to order and determining when the instructions are in out-of-order execution. The buffer alternative name list is used for assigning an item in the first queue memory, filling an instruction pointer of the load instruction in the assigned item, assigning an item in the second queue memory, filling a dependency in the assigned item, and making the subsequently executed load instruction share the dependency. The dependency is used for identifying an instruction upon which the store instruction depends for its data in the assigned item in the second queen memory.

Description

technical field [0001] The present invention relates to out-of-order execution microprocessors, and more particularly to the performance of memory load instructions in out-of-order execution microprocessors. Background technique [0002] The microprocessor has a load instruction (load instruction) for loading data from a source memory location (source memory location) into the temporary register of the microprocessor; and a store instruction for loading data from the temporary register of the microprocessor Store to a destination memory location. Generally, a microprocessor encounters a situation where a load instruction specifies a memory source address equal to an older store instruction's memory destination address. In other words, the earlier store instruction wrote data to the memory address that the load instruction was reading. This situation is often referred to as a store collision. When a store collision occurs, in order to execute the program correctly, the mic...

AI Technical Summary

Problems solved by technology

A potential disadvantage of the color bit array is that it requires a large amount of storage space in the microprocessor since the number of entries in the instruction cache is usually large

A large color bit array can consume a lot of power and physical space in the microprocessor

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