Synchronization method and device of double 2-vote-2 system
A device, a technology for synchronizing interrupts, used in the generation of response errors, redundancy in hardware for error detection of data, instruments, etc., to achieve the effect of realizing dissimilarity, eliminating timing errors, and avoiding common mode errors
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[0034] CPLD: Complex Programmable Logic Device, complex programmable logic device.
[0035] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.
[0036] The core of the present invention is that the system has the same two systems, and the two CPUs in each system that perform the same actions are equipped with internal timers, which are used as the timing clocks for executing tasks. The two CPUs perform the tasks through the internal communication unit. Communication and execute the reset instructio...
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