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Synchronization method and device of double 2-vote-2 system

A device, a technology for synchronizing interrupts, used in the generation of response errors, redundancy in hardware for error detection of data, instruments, etc., to achieve the effect of realizing dissimilarity, eliminating timing errors, and avoiding common mode errors

Active Publication Date: 2012-07-25
CRSC RESEARCH & DESIGN INSTITUTE GROUP CO LTD
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  • Claims
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Problems solved by technology

[0004] However, since there are a large number of security control and measurement tasks based on clock sources in railway signal control, the comparison method based on the same clock of two times two out of two cannot avoid the common mode error caused by the common clock source; in addition, due to This bus-level synchronization method must perform a two-by-two comparison in the same software environment, which cannot avoid potential safety hazards caused by the same specific software and its specific implementation method.

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  • Synchronization method and device of double 2-vote-2 system
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  • Synchronization method and device of double 2-vote-2 system

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Embodiment Construction

[0034] CPLD: Complex Programmable Logic Device, complex programmable logic device.

[0035] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0036] The core of the present invention is that the system has the same two systems, and the two CPUs in each system that perform the same actions are equipped with internal timers, which are used as the timing clocks for executing tasks. The two CPUs perform the tasks through the internal communication unit. Communication and execute the reset instructio...

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Abstract

The embodiment of the invention discloses a synchronization method of a double 2-vote-2 system, the system has two same systems, two CPUs with same actions in each system are both provided with an internal timer as a timing clock when performing a task, and the two CPUs communicate through a communication unit in the systems, execute a reset instruction through the connected timers respectively and control the synchronization of the two CPUs in the systems in combination with a common clock source which can generate high-frequency pulse signals; and simultaneously, the two systems communicatewith each other, CPU synchronization data of a main system is transmitted to a subordinate system, thus carrying out synchronization control between the main system and the subordinate system. The invention also discloses a device corresponding to the method. As each CPU in the system has the independent internal timers and each system has an external timer, through the coordination, a common-mode error caused by sharing a clock in the prior art is effectively avoided, and the two CPUs in the systems can realize the diversity of the hardware with the same function by adopting different software.

Description

Technical field [0001] The invention relates to the technical field of railway signals, and more specifically, to a synchronization method and equipment of a two-by-two-out-of-two system. Background technique [0002] The railway signal control system completes the control function of related signal equipment. It adopts a two-by-two-out-two system with better performance. The system consists of two identical safety control systems. The main system performs control functions, and the slave system guarantees Under the premise of synchronization, it is used as a hot backup to ensure that the normal working process can be completed through the master-slave switchover in the case of a single system failure. In a two-by-two-out-two system, the CPUs in the two systems need to work synchronously to ensure normal operation. Therefore, a reasonable and reliable two-by-two-out system CPU synchronization method is particularly important. [0003] The most commonly used method in the current t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/16G06F13/24
Inventor 张利峰邱兆阳孙寿龙赵晓东周夏芳崔新民张乐平佘晓丽李民陈强卢利勇于长洪
Owner CRSC RESEARCH & DESIGN INSTITUTE GROUP CO LTD
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