Galois field multiplier

Abstract

The invention discloses a Galois field multiplier comprising a multiplication circuit, a memory and a first module, wherein the multiplication circuit is used for inputting two m-digit binary multipliers and outputting the product of the two multipliers; the output of the multiplication circuit includes high-digit output and low-digit output, and m represents the integer power of 2; the memory is used for storing the Galois field multiplication coefficient unit calculated according to the selected Galois field primitive polynomial; and the first module is used for carrying out operations on the output of the multiplication circuit and the Galois field multiplication coefficient unit stored in the memory to obtain the product of the Galois field multiplication of the two m-order binary multipliers. The Galois field multiplier of the invention has the advantages of small hardware area, low latency and high universality.

Description

technical field [0001] The present invention relates to the design of an integrated circuit used in the communication field, in particular to an integrated circuit design of a Galois field multiplier. Background technique [0002] Galois field multiplier (Galois field multiplier) is a special kind of multiplier, and all its calculations are based on finite fields, so it is also called finite field multiplier. Galois field multipliers have been widely used in communication fields such as coding, error correction, and encryption. [0003] There are some processors that can realize the function of Galois field multiplication, and the logic module can also be used to perform Galois field multiplication, or traditional digital signal processors can also be used to implement Galois field multiplication, but these solutions are limited Galois field multiplication is complex and takes a lot of time. In view of its wide range of applications, the Galois field multiplier is often im...

AI Technical Summary

Problems solved by technology

Its advantage is that the response time (latency) of the multiplication output result is small, only 1 clock cycle, but the hardware area is large, and the design complexity is large. When calculating GF(2 m ) multiplication, the logic area of ​​the Bit-Parallel method is O(m 2 )

However, the existing Bit-parallel is generally optimized for a specific primitive polynomial, and many solutions mainly focus on the three-term polynomial, that is, the primitive polynomial, P(x)=x 4 +x+1, such a design lacks versatility

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