Method for constructing copper wire on wafer and chemical mechanical polishing (CMP) method for copper

Abstract

The invention discloses a method for constructing a copper wire on a wafer, which comprises the following steps of: depositing a first interlayer dielectric on the upper surface of the wafer; constructing a second interlayer dielectric on the upper surface of the first interlayer dielectric of the wafer, wherein the hardness of the second interlayer dielectric is lower than that of the first interlayer dielectric; photoetching the second interlayer dielectric and the first interlayer dielectric to define a groove structure, wherein the bottom of the groove structure is positioned in the first interlayer dielectric; sequentially depositing a barrier layer and a copper seed crystal layer on the upper surface of the wafer and the inner wall of a groove; depositing copper on the upper surface of the wafer, wherein the copper is filled in the groove to form the copper wire; and performing chemical mechanical polishing (CMP) on the wafer to reach the first interlayer dielectric so as to make the upper surface of the wafer subjected to planarization. The invention also discloses a CMP method for the copper. The sinking degree of the surface of the copper wire constructed by the scheme of the invention is reduced to a certain extent compared with that of the prior art.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for constructing copper metal lines on a wafer and a copper CMP method. Background technique [0002] In the semiconductor integrated circuit industry, copper is increasingly replacing aluminum as conductive devices or connection pads in semiconductor wafers due to its lower electrical impedance and higher electron mobility compared to aluminum, It can meet the requirements of high frequency, high integration, high power, large capacity and long service life. However, there is no mature copper etching process at present, such as figure 1 The shown process flow constructs copper metal lines on the wafer, including the following steps: Step 101: Depositing an interlayer dielectric (Inner Level Dielectric, ILD) on the surface of the wafer, where the interlayer dielectric is an insulator material. [0003] Step 102: performing photoli...

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Problems solved by technology

[0014] As can be seen from the microscopic cross-sectional change process of the above wafer, a very important reason for the sinking phenomenon at the metal line after CMP is that the hardness difference between copper and the interlayer medium is large. When grinding on the third polishing pad, although The purpose of this step is to remove the barrier layer outside the trench structure, but the MRR of copper will exceed the MMR of the interlayer dielectric and the barrier layer, and excessive copper loss will cause depressions at the metal lines

The depression at the metal line will not only have a bad effect on the conductivity of the metal line, but also damage the flatness of the wafer surface, thus affecting the subsequent processing technology.

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