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Memory errors processing method

An error handling and memory technology, applied in static memory, electrical digital data processing, error detection/correction, etc., which can solve the problem of low price of shadow memory

Active Publication Date: 2014-06-04
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The related method of content addressable memory (CAM) uses shadow memory to redirect the internal DRAM to the external SRAM when an error occurs. However, due to the external circuit and layout area, the price of the shadow memory not cheap

Method used

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Embodiment Construction

[0038] The following describes the preferred embodiment of the present invention. Each embodiment is used to illustrate the principles of the present invention, but not to limit the present invention. The scope of the invention should be determined by the terms of the appended claims.

[0039] example system

[0040] figure 1 Example system 100 employed for embodiments of the present invention. The system 100 includes a system-on-chip (SoC) 120, an application specific integrated circuit (ASIC) 130 external to the SoC 120, and other circuits and software (not shown in the figure for simplicity of description) ). In one embodiment, the system 100 includes a network router or a network switch, but other embodiments of the present invention are not limited to specific applications, and can also be applied to other systems. According to different embodiments, the system 100 can be used to fix bugs, or make other units such as SoC 120, ASIC 130, etc. fix bugs. Additionally,...

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Abstract

Redundancy including extra rows and / or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list. When another error occurs, it is determined whether its failed address is on the stored list. If it is not, then the error is again assumed to be a soft error, the data at this location is corrected, and the failed address is added to the stored address list, etc. If, however, the failed address is already in the stored failed address list, the error is considered either a latent error or VTR, and is repaired on the fly using on-chip redundancy.

Description

technical field [0001] The present invention relates to memory errors. Embodiments use Error Checking and Correcting (ECC) and redundancy row and redundancy column to repair latent errors and VRT errors. Background technique [0002] Various forms of errors often occur in memory. Soft errors, usually caused by alpha particles in semiconductor packages and neutrons in the environment. VRT occurs when a bit is sometimes weak and sometimes strong. This phenomenon will cause the device to fail from time to time even though it can pass the final test (such as the test done by the chip manufacturer before the device leaves the factory). VRTs have many similar phenomena to soft errors, except that VRTs typically recur on fixed addresses in memory. The performance of semiconductor circuits degrades over time due to an electrical short between the gate and drain of the transistor that stores a bit. These errors occurring in the memory cause latent failures that can cause the devi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/42
CPCG11C2029/0409G11C2029/0401G06F11/1048G11C2029/0411G11C29/44G11C2029/1208G11C29/76G11C29/4401G11C29/42
Inventor 戈马克·麦克·康乃尔
Owner TAIWAN SEMICON MFG CO LTD