Array substrate and manufacturing method thereof
An array substrate and substrate technology, applied in the field of liquid crystal display manufacturing, can solve problems such as lowering display quality, polluting air bubbles, poor display of liquid crystal display panels, etc., and achieve the effect of ensuring display quality
Active Publication Date: 2012-09-26
BOE TECH GRP CO LTD +1
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- Description
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- Application Information
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Problems solved by technology
As the electrochemical reaction progresses, the common electrode layer 4 is gradually corroded. When the corroded area of the common electrode layer 4 is large enough, the common electrode voltage provided by the common electrode layer 4 will be abnormal, thereby causing the liquid crystal display panel to drop. Display defects appear in the edge area, reducing the display quality
When the common electrode layer 4 is severely corroded, it may even affect the sealant area 8, resulting in liquid crystal (Liquid Crystal, abbreviated: LC) pollution and bubbles in the sealant area 8, thereby further reducing the display quality
Method used
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Embodiment Construction
[0030] Embodiment 1 of the present invention provides an array substrate. The array substrate includes a display area and a frame area around the display area. The structure and positional relationship between the display area and the frame area can be found in figure 1 shown in . In this embodiment, the frame area includes: a substrate, a common electrode layer located on the substrate, a via hole formed on the protective layer and located on the common electrode layer, a transparent conductive layer located on the protective layer and filled in the via hole. Layer, the isolation line formed on the common electrode layer and the protective layer and on the substrate, the isolation line is located outside the via hole and inside the sealant area, the sealant area is located on the transparent conductive layer and the sealant The sealant in the glue area is filled in the isolation line.
[0031] Specifically, taking the lower edge area of the frame area as an example, the lo...
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Abstract
The invention discloses an array substrate and a manufacturing method thereof. The array substrate comprises a display area and a border area which is arranged at the periphery of the display area, and the border area comprises a substrate, a common electrode layer arranged above the substrate, a protective layer arranged above the common electrode layer, a through hole which is formed on the protection layer and is arranged above the common electrode layer, a transparent conducting layer which is arranged above the protection layer and is filled in the through hole, and a shielding wire which is formed on the common electrode layer and the protection layer and is arranged above the substrate, wherein the shielding wire is arranged at the outer side of the through hole and the inner side of a border sealing glue area, the border sealing glue area is arranged above the transparent conducting layer and the border sealing glue of the border sealing glue area is filled in the shielding wire. In the technical scheme in the invention, the display quality of the lower edge area can be effectively ensured.
Description
technical field [0001] The invention relates to the field of manufacturing liquid crystal displays, in particular to an array substrate and a manufacturing method thereof. Background technique [0002] With the development of liquid crystal display technology, TFT LCD with low power consumption and no radiation has become the mainstream of the liquid crystal display market. figure 1 is a schematic structural diagram of a liquid crystal display panel in the prior art, figure 2 for figure 1 The partial enlargement in the image 3 for figure 2 Middle A-A sectional view, such as figure 1 , figure 2 and image 3 as shown, figure 1 The array substrate of the liquid crystal display panel includes a display area 1 and a frame area around the display area 1 , and the frame area includes an upper edge area 21 , a left edge area 22 , a lower edge area 23 and a right edge area 24 . The upper edge area 21 and the left edge area 22 of the frame area are integrated circuit board...
Claims
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IPC IPC(8): G02F1/1362G02F1/1368H01L21/82H01L23/31
Inventor 张志男梁国鹏
Owner BOE TECH GRP CO LTD