Cell switching method and cell switching device

Abstract

The invention discloses a cell switching method and a cell switching device and relates to data communication technology. In the embodiment of the invention, a fifo (First In First Out) is added at each input port, the cell input to the corresponding input end is cached, the cell cached in each fifo is split into a plurality of data blocks and written into a shared cache, and an output port reads and outputs the cell through different time gaps to finish switching. As the fifo is added to cache the cell, different ports can respectively read and write at different time gaps when ports need to read and write the same cache, thus avoiding confliction and being easy in scheduling.

Description

technical field [0001] The present invention relates to data communication technology, in particular to a cell exchange method and device in data communication technology. Background technique [0002] In current switching devices, switching chips are generally implemented using two architectures, one is a crossbar (crossbar switch matrix) architecture, and the other is a shared-memory (shared memory) architecture. [0003] Using the crossbar architecture for cell exchange needs to consider the two-level scheduling problem of data input and output. The input and output need to be matched, that is, the input and output terminals need to be matched and scheduled according to their own idle conditions, and then negotiate with each other. The complexity of the scheduling algorithm increases exponentially with the increase of the input and output ports. When there are many input and output ports, the complexity of the scheduling algorithm is extremely high. [0004] On the basis...

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Problems solved by technology

The complexity of the scheduling algorithm increases exponentially with the increase of input and output ports. When there are many input and output ports, the complexity of the scheduling algorithm is extremely high.

[0004] On the basis of this crossbar architecture, the crossbar structure with crosspoint buffer is further developed to add a cache at each crosspoint. Although the matching algorithm is no longer required, the number of crosspoint caches required is the square of the number of input and output ports. times, in the case of a large number of ports, the number of cross-point buffers reaches an unrealizable level

[0005] The share-memory architecture uses a shared cache, which reduces the consumption of cache resources compared to the crossbar architecture. However, when cells are written to multiple shared caches, they are written in turn according to the depth of each cache, so that The depth of each cache is uniform, but this may cause different output ports to read data from the same cache at the same time, causing conflicts

If you increase the bandwidth of the shared cache and allow more output ports to read data at the same time, the probability of such conflicts can be reduced, but at the same time, the scheduling complexity when multiple output ports need to read data in the unified cache also increases. When the number of ports is large, it is difficult to resolve conflicts

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