On-line upgrading method and device of configuration file of field-programmable gate array (FPGA)

Abstract

The invention discloses an on-line upgrading method and an on-line upgrading device of a configuration file of a field-programmable gate array (FPGA) and is used for accomplishing the on-line upgrading of the configuration file of the FPGA on the premise of no arrangement of an additional logic device and fulfilling the aim that the FPGA can be used after being energized. The on-line upgrading method of the configuration file of the FPGA comprises the following steps that: during the upgrading of the configuration file of the FPGA, a central processing unit (CPU) controls a bus changeover switch to switch off a first data channel between the FPGA and a memory and switch on a second data channel between the CPU and the memory; the CPU updates the configuration file, which is memorized in the memory, of the FPGA; after the configuration file of the FPGA is updated, the CPU controls the bus changeover switch to switch on the first data channel and switch off the second data channel; and the CPU triggers the FPGA to re-load the updated configuration file of the FPGA from the memory, and the FPGA performs configuration.

Description

Technical field [0001] The present invention relates to the technical field of electronic circuit design, in particular to an online upgrade method and device for FPGA configuration files. Background technique [0002] Field-Programmable Gate Array (FPGA, Field-Programmable Gate Array) is used in Programmable Array Logic (PAL, Programming Array Logic), General Array Logic (GAL, Generic Array Logic), Complex Programmable Logic Device (CPLD, Complex Programmable Logic) Device) is a product of further development. It allows the personnel involved to use the hardware description language (Verilog or VHDL) to complete the circuit design, and generate the configuration file through the compilation of the corresponding synthesis tool. When the FPGA loads the configuration file, the FPGA can realize the logic functions required by the design. [0003] When the FPGA loads the configuration file, you can use the Joint Test Action Group (JTAG) download cable to connect to its JTAG interface,...

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Problems solved by technology

[0007] In the above two solutions, there are the following problems: In the above-mentioned first solution, a special CPLD device needs to be added, and the CPLD needs to simulate the timing of the interface between the CPU and the memory, and the timing of configuring the FPGA, which takes up more time for the CPLD. Pins consume logical resources; in the second solution above, more processing resources of the resource-intensive CPU need to be occupied. Moreover,

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