Power supply management circuit

Abstract

The invention discloses a power supply management circuit which is used to provide a predetermined voltage to a memory cell. The power supply management circuit comprises: a first transistor, a second transistor, a first input terminal, a second input terminal and an output terminal. A source electrode of the first transistor is connected with a power supply terminal VCC. A grid electrode of the first transistor is connected with a drain electrode of the second transistor and is connected with the first input terminal. The drain electrode of the first transistor is connected with the source electrode of the second transistor and is connected with the output terminal. The grid electrode of the second transistor is connected with the second input terminal. The first input terminal and the second input terminal provide a logic control signal. By using the power supply management circuit, storage circuit power consumption can be reduced and simultaneously a maintenance capability to data can be increased. And an area occupied by the power supply management circuit is small.

Description

technical field [0001] The invention relates to a power management circuit, in particular to a power management circuit applied to a storage unit. Background technique [0002] With the continuous improvement of the CMOS process level, the continuous reduction of the minimum feature size, and the continuous reduction of the threshold voltage, memory devices present two problems that cannot be ignored: the continuous increase of leakage current and the loss of data in a stable state. If the above problems cannot be considered, logical errors and functional failures will inevitably occur in some cases. [0003] At present, the power consumption generated by the memory accounts for an important proportion of the power consumption of the SOC (System-on-a-Chip) chip, and with the progress of the technology, it will account for a larger proportion. Therefore, the problem of memory power consumption has caused widespread attention. In order to reduce memory power consumption, the...

AI Technical Summary

Problems solved by technology

[0002] With the continuous improvement of the CMOS process level, the continuous reduction of the minimum feature size, and the continuous reduction of the threshold voltage, memory devices present two problems that cannot be ignored: the continuous increase of leakage current and the loss of data in steady state

However, since the size of P1 and P2 needs to be adjusted very large in this kind of circuit to realize its function, it will occupy a considerable area when it is applied to more cell arrays.

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