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Delay-locked loop

A delay-locked loop and delay unit technology, applied in the field of delay-locked loops, can solve problems such as limiting delay control accuracy and affecting VCDL delay consistency, and achieve the effect of improving delay control accuracy

Active Publication Date: 2012-09-19
WUXI ZGMICRO ELECTRONICS CO LTD
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Problems solved by technology

However, when the two selected signals are in two different muxes, the load change will produce a sudden change. This sudden change is manifested as an obvious jump in the delay step during the switching process in the simulation. This situation will Limit the accuracy of delay control, affecting the consistency of delay at all levels of VCDL

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Embodiment Construction

[0040] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0041] In order to enable those skilled in the art to better understand the present invention, the following further describes the simulation and analysis process of the problem of inconsistency of delay times of VDCL levels found by the inventor of the present patent.

[0042] refer to figure 1 , it is assumed that the VCDL is composed of N delay units, which are 1, 2, 3, 4, ..., i, i+1, ... N-1, N. Among them, the output signal of the i-th delay unit is denoted as n i , at the same time, it is also the input signal of the i+1th unit. Since the DLL is mostly a high-speed circuit in actual use, the delay unit mostly uses an analog delay unit, and its output waveform is between a sine wave and a square wave. Mux generally uses a...

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Abstract

The invention discloses a delay-locked loop which comprises a voltage-controlled delay line and a multiplexer, wherein the voltage-controlled delay line comprises multiple cascaded delay units; the multiplexer comprises multiple input tube pairs; each input tube pair comprises a first input tube and a second input tube in series connection; the multiplexer also comprises a switch connected between the first input tube and a sharing current source of a power voltage end, a first switch group consisting of the switches connected between the second input tube and a sharing current source of a grounding voltage end, a switch connected at one end of the first input tube away from the power voltage, and a second switch group consisting of the switches connected at one end of the second input tube away from the grounding voltage; and the output end node of the multiplexer is located between the two switches of the second switch group. The delay-locked loop disclosed by the invention can improve the delay control precision and ensure the consistency of all levels of delay of VCDL (voltage-controlled delay line).

Description

[0001] This application is a divisional application with an application date of January 08, 2010, an application number of 201010033860.7, and an invention title of "a delay phase-locked loop". technical field [0002] The invention relates to the field of delay circuit design, in particular to a delay phase-locked loop. Background technique [0003] In recent years, with the rapid development of semiconductor technology, digital signal processing technology and communication technology, the integration density of the chip is getting higher and higher, the scale is getting bigger and the working speed is getting faster and faster, which makes the important part of the chip The quality of the on-chip clock is more important. Because the unconditionally stable delay locked loop (delay locked loop-DLL) has the characteristics of "zero delay", low noise, low jitter (iitter) and easy design, it is suitable for clock synchronization of large-scale high-speed chips. [0004] The c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/08
Inventor 高峻
Owner WUXI ZGMICRO ELECTRONICS CO LTD