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Delay phase locked loop

A delay-locked loop and delay unit technology, applied in the field of delay-locked loops, can solve problems such as limiting delay control accuracy, affecting VCDL delay consistency, etc., to achieve the effect of improving delay control accuracy

Inactive Publication Date: 2012-10-17
WUXI ZGMICRO ELECTRONICS CO LTD
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  • Claims
  • Application Information

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Problems solved by technology

However, when the two selected signals are in two different muxes, the load change will produce a sudden change. This sudden change is manifested as an obvious jump in the delay step during the switching process in the simulation. This situation will Limit the accuracy of delay control, affecting the consistency of delay at all levels of VCDL

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Embodiment Construction

[0026] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0027] In order to enable those skilled in the art to better understand the present invention, the following further describes the simulation and analysis process of the problem of inconsistency of delay times of VDCL levels found by the inventor of the present patent.

[0028] refer to figure 1 , it is assumed that the VCDL is composed of N delay units, which are 1, 2, 3, 4, ..., i, i+1, ... N-1, N. Among them, the output signal of the i-th delay unit is denoted as n i , at the same time, it is also the input signal of the i+1th unit. Since the DLL is mostly a high-speed circuit in actual use, the delay unit mostly uses an analog delay unit, and its output waveform is between a sine wave and a square wave. Mux generally uses a...

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Abstract

The invention discloses a delay phase locked loop, which comprises a voltage control delay line and a multiplexer. The voltage control delay line comprises a plurality of cascade delay units, the multiplexer comprises a plurality of differential pair tubes, the grid of each differential pair tube is respectively connected with the output node of one delay unit, one end of the differential pair tube is connected with a grounding voltage by a shared current source, and the other end thereof is connected with a power supply voltage by a load device. The multiplexer further comprises a first switch connected among the differential pair tubes and the shared current source, a second switch connected among the differential pair tubes and the load device, and the output end node of the multiplexer is arranged between the second switch and the load device. The invention can improve the precision of delay control and ensure the consistency of the delay of each stage for VCDL.

Description

technical field [0001] The invention relates to the field of delay circuit design, in particular to a delay phase-locked loop. Background technique [0002] In recent years, with the rapid development of semiconductor technology, digital signal processing technology and communication technology, the integration density of the chip is getting higher and higher, the scale is getting bigger and the working speed is getting faster and faster, which makes the important part of the chip The quality of the on-chip clock is more important. Because the unconditionally stable delay locked loop (delay locked loop-DLL) has the characteristics of "zero delay", low noise, low jitter (iitter) and easy design, it is suitable for clock synchronization of large-scale high-speed chips. [0003] The core component of a delay-locked loop (DLL) is a voltage-controlled delay line (VCDL), and its main function is to generate multiple (such as 1 to i) delays with the original signal for a certain t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/08
Inventor 高峻
Owner WUXI ZGMICRO ELECTRONICS CO LTD