Strain SiGe square-in-square type channel BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and preparation method thereof

A technology of integrated devices and channel direction, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc. issues such as increased complexity

Inactive Publication Date: 2012-10-24
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with the further increase of the scale of integrated circuits, the reduction of device feature size, the increase of integration and complexity, especially after the device feature size enters the nanometer scale, the limitations of materials and physical characteristics of Si CMOS devices have gradually emerged. out, limiting the further development of Si integrated circuits and their manufacturing processes
Although microelectronics has made great progress in the research and application of compound semiconductors and other new materials in some fields, it is far from having the conditions to replace silicon-based processes

Method used

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  • Strain SiGe square-in-square type channel BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0139] Embodiment 1: The preparation of the strained SiGe back channel BiCMOS integrated device and circuit with a conductive channel of 45nm, the specific steps are as follows:

[0140] Step 1, epitaxial growth.

[0141] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;

[0142] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 .

[0143] Step 2, deep trench isolation preparation.

[0144] (2a) Using chemical vapor deposition (CVD), grow a layer of SiO with a thickness of 500 nm on the surface of the epitaxial Si layer at 800 °C. 2 Floor;

[0145] (2b) Photo...

Embodiment 2

[0221] Embodiment 2: The preparation of the strained SiGe back channel BiCMOS integrated device and circuit with a conductive channel of 30nm, the specific steps are as follows:

[0222] Step 1, epitaxial growth.

[0223] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 300nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;

[0224] (1b) Using chemical vapor deposition (CVD), grow an N-type epitaxial Si layer with a thickness of 80nm on the upper Si material at 700°C as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 .

[0225] Step 2, deep trench isolation preparation.

[0226] (2a) Using chemical vapor deposition (CVD), grow a layer of SiO with a thickness of 400 nm on the surface of the epitaxial Si layer at 700 °C. 2 Floor;

[0227] (2b) Photoetched deep trench isolation regi...

Embodiment 3

[0303] Embodiment 3: The preparation of the strained SiGe back channel BiCMOS integrated device and circuit with a conductive channel of 22nm, the specific steps are as follows:

[0304] Step 1, epitaxial growth.

[0305] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 150nm, and the upper material is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;

[0306] (1b) Using the chemical vapor deposition (CVD) method, at 600 ° C, grow a layer of N-type epitaxial Si layer with a thickness of 50 nm on the upper Si material, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 .

[0307] Step 2, deep trench isolation preparation.

[0308] (2a) Using chemical vapor deposition (CVD), grow a layer of SiO with a thickness of 300 nm on the surface of the epitaxial Si layer at 600 °C. 2 Floor;

[0309] (2b) Photoetched de...

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Abstract

The invention discloses a strain SiGe square-in-square type channel BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and a preparation method thereof. The preparation method comprises the steps of: growing an N type epitaxial layer on an SOI (Silicon On Insulator) substrate to be used as a bipolar device collector region, preparing a deep channel for isolation, then sequentially preparing a base electrode polycrystalline, a base region, an emitter region and a collector electrode to form a SiGe HBT (Heterojunction Bipolar Transistor) device; growing five layers of materials in a substrate NMOS (N-channel Metal Oxide Semiconductor) device active region, preparing a drain electrode, a grid electrode and an active region to process an NMOS device; growing three layers of materials in a PMOS (P-channel Metal Oxide Semiconductor) device active region, preparing a virtual grid electrode, carrying out injection by using an automatic alignment process to form PMOS device source region and drain region; etching the virtual grid electrode to prepare a PMOS device, and forming the strain SiGe square-in-square type channel BiCMOS integrated device and a circuit. According to the invention, in a preparation process, by adopting the fully-automatic alignment process, parasitic resistance and capacitance are effectively reduced, current and frequency characteristics of the device are improved; and an emitter electrode, a base electrode and a collector electrode of a SiGe HBT (Heterojunction Bipolar Transistor) are all made of polycrystalline, thus the area of a device active region and the size of the device are reduced, and the integration of the circuit is increased.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to a strained SiGe back channel BiCMOS integrated device and a preparation method. Background technique [0002] Semiconductor integrated circuits are the foundation of the electronics industry, and people's huge demand for the electronics industry has prompted the rapid development of this field. In the past few decades, the rapid development of the electronics industry has had a huge impact on social development and national economy. At present, the electronics industry has become the largest industry in the world, occupying a large share in the global market, and its output value has exceeded 1 trillion US dollars. [0003] Si CMOS integrated circuits have the advantages of low power consumption, high integration, low noise and high reliability, and occupy a dominant position in the semiconductor integrated circuit industry. However, with the further i...

Claims

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): H01L27/06H01L21/8249
Inventor胡辉勇宋建军宣荣喜舒斌张鹤鸣李妤晨吕懿郝跃
OwnerXIDIAN UNIV