Strain SiGe HBT (Heterojunction Bipolar Transistor) vertical channel BiCMOS integrated device and preparation method thereof

A vertical channel and integrated device technology, applied in the field of vertical channel BiCMOS integrated devices and its preparation, and strained SiGe HBT, can solve the problem of increasing the integration degree and complexity of device feature size, the lack of conditions for replacing silicon-based processes, and the limitation of Si Integrated circuit manufacturing process development and other issues, to achieve the effect of performance enhancement

Inactive Publication Date: 2015-01-21
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with the further increase of the scale of integrated circuits, the reduction of device feature size, the increase of integration and complexity, especially after the device feature size enters the nanometer scale, the limitations of materials and physical characteristics of SiCMOS devices have gradually emerged. , limiting the further development of Si integrated circuits and their manufacturing processes
Although microelectronics has made great progress in the research and application of compound semiconductors and other new materials in some fields, it is far from having the conditions to replace silicon-based processes

Method used

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  • Strain SiGe HBT (Heterojunction Bipolar Transistor) vertical channel BiCMOS integrated device and preparation method thereof

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0134] Embodiment 1: The strained SiGe HBT, vertical channel BiCMOS integrated device and circuit of 45nm conductive channel are prepared, and the specific steps are as follows:

[0135] Step 1, epitaxial growth.

[0136] (1a) Select the doping concentration to be 5×10 14 cm -3 A P-type Si sheet as a substrate;

[0137] (1b) Thermally oxidize a layer of SiO with a thickness of 300nm on the substrate surface 2 Floor;

[0138] (1c) Photolithography of the buried layer region, implanting N-type impurities into the buried layer region, and annealing at 800°C for 90 minutes to activate the impurities to form an N-type heavily doped buried layer region;

[0139] (1d) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 2 μm on the upper layer of Si material at 600 ° C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 ;

[0140] (1e) Deposit a layer of SiO with a thickness of 200nm on the su...

Embodiment 2

[0214] Embodiment 2: The conductive channel is prepared as a strained SiGe HBT, a vertical channel BiCMOS integrated device and a circuit, and the specific steps are as follows:

[0215] Step 1, epitaxial growth.

[0216] (1a) Select the doping concentration as 1×10 15 cm -3 A P-type Si sheet as a substrate;

[0217] (1b) Thermally oxidize a layer of SiO with a thickness of 400nm on the substrate surface 2 Floor;

[0218] (1c) Photoetching the buried layer region, implanting N-type impurities into the buried layer region, and annealing at 900°C for 60 minutes to activate the impurities to form an N-type heavily doped buried layer region;

[0219] (1d) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 2.5 μm on the upper layer of Si material at 700 ° C, as the collector region, and the doping concentration of this layer is 5 ×10 16 cm -3 ;

[0220] (1e) Deposit a layer of SiO with a thickness of 240nm on the surface of...

Embodiment 3

[0294] Embodiment 3: The strained SiGe HBT, vertical channel BiCMOS integrated device and circuit of 22nm conductive channel are prepared, the specific steps are as follows:

[0295] Step 1, epitaxial growth.

[0296] (1a) Select the doping concentration to be 5×10 15 cm -3 A P-type Si sheet as a substrate;

[0297] (1b) Thermally oxidize a layer of SiO with a thickness of 500nm on the surface of the substrate 2 Floor;

[0298] (1c) Photolithography of the buried layer region, implanting N-type impurities into the buried layer region, and annealing at 950°C for 30 minutes to activate the impurities to form an N-type heavily doped buried layer region;

[0299] (1d) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 3 μm on the upper layer of Si material at 750 ° C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 ;

[0300] (1e) Deposit a layer of SiO with a thickness of 300nm on the...

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Abstract

The invention discloses a strain SiGe HBT (Heterojunction Bipolar Transistor) vertical channel BiCMOS integrated device and a preparation method thereof. The preparation method comprises the following steps of: firstly preparing a buried layer on a Si substrate slice, growing N-Si as a bipolar device collector region, photoetching a base region, growing P-SiGe, i-Si and i-Poly-Si in the base region, preparing a deep groove for isolation, and forming an emitting electrode, a base electrode and a collector electrode to form a SiGe HBT device; respectively growing an N-type Si epitaxial layer, an N-type strain SiGe layer, a P-type strain SiGe layer, an N-type strain SiGe layer, an N-type Si layer and the like in active regions of a substrate NMOS device and a PMOS device, and preparing a drain electrode, a grid electrode and a source region in an active region of the NMOS device to complete the preparation of the NMOS device; preparing a virtual grid electrode in the active region of the PMOS device to form the source and drain of the PMOS device; and etching the virtual grid electrode to complete the preparation of the PMOS device, and forming the BiCMOS integrated device a circuit. By fully utilizing the characteristics that the electron mobility in the vertical direction and the hole mobility in the horizontal direction of a strain SiGe material are higher than those of relaxation Si, the preparation method can be used for manufacturing the strain SiGe HBT vertical channel BiCMOS integrated circuit with enhanced performance by using a low-temperature process.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a strained SiGe HBT, a vertical channel BiCMOS integrated device and a preparation method. Background technique [0002] Semiconductor integrated circuits are the foundation of the electronics industry, and people's huge demand for the electronics industry has prompted the rapid development of this field. In the past few decades, the rapid development of the electronics industry has had a huge impact on social development and national economy. At present, the electronics industry has become the largest industry in the world, occupying a large share in the global market, and its output value has exceeded 1 trillion US dollars. [0003] SiCMOS integrated circuits have the advantages of low power consumption, high integration, low noise and high reliability, and occupy a dominant position in the semiconductor integrated circuit industry. Howev...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H01L27/06H01L21/28H01L21/8249
Inventor宋建军胡辉勇舒斌王海栋张鹤鸣宣荣喜郝跃
OwnerXIDIAN UNIV