Universal multi-operand summator

Abstract

The invention discloses a universal multi-operand summator which can be used for achieving synchronous parallel adding of multiple multi-digit binary numbers in the digital arithmetical computation field. The universal multi-operand summator comprises a module 110, a module 120 and a module 130, and the module 110 uses a switching circuit for achieving parallel adding of multiple single-digit binary numbers from structural aspect. Adding of two single-digit numbers and single-digit carry numbers is also achieved by the module 120 through the switching circuit. The module 130 is composed of the module 110, the module 120 and the like, and carry computation and transmission exceeding the operand digital number is completed. Synchronous parallel computation of operand values corresponding to all digit rights is carried out by using the module 110, then according to digit right correspondence, addition numbers are regrouped based on a computation result, the module 110 is used again until that each digit right only has two addition numbers after regrouping, carry generation and transmission are achieved through the module 130, and a final addition sum is acquired by the module 120. The universal multi-operand summator is simple in circuit structure and neat in design, and a large amount of time and hardware cost can be reduced.

Description

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AI Technical Summary

Benefits of technology

This patented technology addresses problems associated with current methods for implementing digital signal processing (DSP) systems that require complex logic operations or switches between different modes during data transmission. These techniques have led to increased complexity and costly software configurations. However, they solve this issue by allowing more efficient ways to process signals at once.

Problems solved by technology

Technologies described in this patented technical problem addressed in this text include improving the efficiency and accuracy of carrying out complex calculations while minimizing hardware requirements without sacrificially increasing processing delays. Current methods require expensive components like transistors, buffers, counters, and other devices, leading to increased complexity and reduced overall functionality. Additionally, conventional designs may lead to overall, the goal being achieved is finding ways to improve the efficiency, precision, size, power consumption, and timing capabilities of implementing multiply operator functions within electronic computers.

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