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High-voltage element and manufacturing method thereof

A technology of high-voltage components and manufacturing methods, applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems such as increasing process steps, reducing the breakdown protection voltage of high-voltage components, and limiting the application range of components

Active Publication Date: 2015-03-25
RICHTEK TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] LDMOS and DDDMOS components are high-voltage components, that is, they are designed to supply higher operating voltages, but when high-voltage components need to be integrated on the same substrate with generally lower operating voltage components, in order to cooperate with lower operating voltage components The process requires the same ion implantation parameters to produce high-voltage components and low-voltage components, so that the ion implantation parameters of high-voltage components are limited, thus reducing the breakdown protection voltage of high-voltage components and limiting the application range of components
If the breakdown protection voltage of the high-voltage components is not sacrificed, it is necessary to increase the process steps and make the high-voltage components in steps with different ion implantation parameters, but this will increase the manufacturing cost in order to achieve the desired breakdown protection voltage.

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  • High-voltage element and manufacturing method thereof
  • High-voltage element and manufacturing method thereof
  • High-voltage element and manufacturing method thereof

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Embodiment Construction

[0035] The drawings in the present invention are all schematic, mainly intended to represent the manufacturing process steps and the upper and lower sequence relationship between each layer, as for the shape, thickness and width, they are not drawn to scale.

[0036] see image 3 , shows the first embodiment of the present invention, and this embodiment shows a schematic cross-sectional view of the application of the present invention to an LDMOS device. In the substrate 11, an insulating region 12 is formed to define the element region 100, wherein the substrate 11 is, for example, P-type but not limited to P-type (it may also be N-type in other implementation forms); the insulating region 12 is, for example, an STI structure or The region oxidizes the LOCOS structure as shown in the figure, and the substrate 11 includes an N-type (or P-type in other implementations) buried layer 14 whose conductivity type is different from that of the substrate 11 . In addition, if image ...

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Abstract

The invention provides a high-voltage element and a manufacturing method thereof. The high-voltage element is formed in a first conducting substrate. The high-voltage element comprises a second conducting buried layer, a first conducting well region and a second conducting well region, wherein the second conducting buried layer is formed in the first conducting substrate; when viewed by a cutaway view, the first conducting well region is positioned between the upper surface of the substrate and the second conducting buried layer; the second conducting well region is in a different position from the first conducting well region in the horizontal direction and is adjacent to the first conducting well region; the second conducting well region comprises a well region lower surface; the well region lower surface is provided with a first part and a second part; the first part is positioned above the second conducting buried layer and electrically coupled with the second conducting buried layer; and the second part is not positioned above the second conducting buried layer and forms a PN junction with the first conducting substrate.

Description

technical field [0001] The invention relates to a high-voltage component and a manufacturing method thereof, in particular to a high-voltage component with enhanced breakdown protection voltage and a manufacturing method thereof. Background technique [0002] figure 1 A cross-sectional view of a lateral double diffused metal oxide semiconductor (LDMOS) device in the prior art is shown. Such as figure 1 As shown, there are a plurality of insulating regions 12 in the P-type substrate 11 to define the device region 100. The insulating regions 12 are, for example, shallow trench isolation (shallow trench isolation, STI) structures or local oxidation of regions as shown in the figure. silicon, LOCOS) structure; the P-type substrate 11 also includes an N-type buried layer 14 . The LDMOS device is formed in the device region 100 , which includes a gate 13 , a drain 15 , a source 16 , a P-well 17 , and an N-type well 18 in addition to the N-type buried layer 14 . Wherein, the N-...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
Inventor 黄宗义朱焕平
Owner RICHTEK TECH