Electric mirror three-dimensional reconstruction method based on SIRT (simultaneous iterative reconstruction technique) algorithm and utilizing CPU (central processing unit)+MIC (many integrated core) cooperative computing mode

A 3D reconstruction and algorithm technology, applied in computing, 3D modeling, processor architecture/configuration, etc., can solve problems such as large amount of computation

Inactive Publication Date: 2013-02-27
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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AI Technical Summary

Problems solved by technology

[0006] The SIRT (joint iterative reconstruction) algorithm has a better reconstruction effect among all image reconstruction algorithms, but it has a huge amount of calculation, so it is necessary to improve the calculation efficiency to meet the needs of fast image reconstruction

Method used

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  • Electric mirror three-dimensional reconstruction method based on SIRT (simultaneous iterative reconstruction technique) algorithm and utilizing CPU (central processing unit)+MIC (many integrated core) cooperative computing mode
  • Electric mirror three-dimensional reconstruction method based on SIRT (simultaneous iterative reconstruction technique) algorithm and utilizing CPU (central processing unit)+MIC (many integrated core) cooperative computing mode

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Embodiment

[0029] For the above analysis, the present invention provides an embodiment of an electron microscope three-dimensional reconstruction parallel method based on the SIRT algorithm and using the CPU+MIC collaborative computing mode, including the following steps:

[0030] Step 1: Build CPU+MIC Collaborative Computing Framework

[0031] On a single node, there are a total of M+1 devices (one CPU+M MIC cards), and the fork-join mode of OpenMP is used to build the framework on a single node. When the program starts to execute, only one main thread exists, which needs to be parallelized. When calculating, the main thread derives additional threads, that is, M+1 OpenMP threads are enabled, and each actively distributes and reads input data through the while(1) loop. Processes 0~M-1 control all MIC devices, and M Threads control CPU devices.

[0032] For example, in this patent, on the CPU+2MICs platform, the main thread controls the dynamic distribution of input data, thread 0 contr...

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Abstract

The invention provides an electric mirror three-dimensional reconstruction method based on the SIRT (simultaneous iterative reconstruction technique) algorithm and utilizing a CPU (central processing unit)+MIC (many integrated core) cooperative computing mode. A CPU terminal is used for dividing an object in an image required to be subjected to iterative reconstruction into slicing units, transmitting values required in reconstruction to an MIC card, performing framework building, task scheduling and parameter initialization of the CPU+MIC cooperative computing mode, and performing dynamic participation on a calculation task of the whole three-dimensional image construction by sequentially acquiring a reconstructed image value of a slice through a reprojection algorithm and a rear projection algorithm in an Openmp multi-thread mode; and an MIC many-core coprocessor is used for sequentially calculating the acquired reconstructed image value of the slice through the reprojection algorithm and the rear projection algorithm in multi-thread and parallel manners according to the reconstructed image value of the slice and a projected image value of the slice acquired by measuring, and performing calculation by adopting the Openmp multi-thread mode on the MIC card.

Description

technical field [0001] The present invention relates to the field of computer application technology, in particular to a 3D image reconstruction method for an electron microscope based on the SIRT algorithm and using a CPU+MIC collaborative computing mode, and especially relates to the use of a CPU+MIC collaborative computing mode for electron microscopy on a MIC many-core architecture Method and device for three-dimensional reconstruction. Background technique [0002] MIC (Many Integrated Core) is a many-core processor launched by Intel Corporation. Compared with the general-purpose multi-core Xeon processor, the MIC many-core architecture has smaller cores and hardware threads, and the many-core processor has higher computing resource density. On-chip communication overhead is significantly reduced, and more transistors and energy are available for more complex parallel applications. Intel MIC products are based on the X86 architecture, based on heavy-core many-core proc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T17/00G06T1/20
Inventor 卢晓伟张清
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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