A Method for Capacitance Extraction of Interconnect Structure

Abstract

The invention provides a capacitance extraction method for an interconnection structure. The method is applied to a conductor, a conductor surface comprises a plurality of triangular boundary elements, and at least one variable point is arranged in each triangular boundary element. The method comprises the following steps of: acquiring coordinates of the variable points of each triangular boundary element; setting an independent random variable and a dependent random variable at each variable point, wherein each independent random variable represents a variation in a direction perpendicular to the surface of the corresponding variable point, and each dependent random variable represents force transmitted to the corresponding variable point by a variation in a second direction; adding each independent random variable and the corresponding dependent random variable into the coordinates of the corresponding variable point to form an equivalent conductor surface; and calculating the equivalent capacitance of the equivalent conductor surface. The triangular boundary elements are used for dispersing the conductor surface mainly without increase of the number of random variables; and the variations of the conductor surface can be timely reflected, and real characteristics of varied capacitance can be accurately reflected by capacitance extraction.

Description

technical field [0001] The invention relates to integrated circuit technology, in particular to a method for extracting capacitance from an interconnection structure. Background technique [0002] The interconnection of integrated circuits at the deep submicron and nanoscale has replaced transistors as the main factor determining the performance of integrated circuits. The electromagnetic parasitic effects of interconnections determine the delay time of integrated circuits, and also affect signal integrity and power consumption. Significant, therefore, the electromagnetic parasitic effects of interconnection lines, circuit models and analysis become the focus of computer-aided design of integrated circuits. Interconnection parasitic extraction (parasitic extraction) is the premise of interconnection analysis. It expresses the electromagnetic parasitic effect as circuit elements such as resistance, capacitance and inductance. Among them, the extraction of resistance is relati...

AI Technical Summary

Problems solved by technology

[0008] The technical problem to be solved by the present invention is to provide a method for extracting the capacitance of the interconnection structure, which is used to solve the problem that the conductor surface of the interconnection structure in the prior art is discontinuous, and the change of the conductor surface area cannot be reflected in time. Extraction of defects that are difficult to accurately reflect the true characteristics of variable capacitance

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