Compact Charge Transfer Refresh Circuit and Refresh Method

Abstract

The invention belongs to the technical field of memories and especially relates to a compact charge transfer refresh circuit and a refresh method thereof. The compact charge transfer refresh circuit comprises an array of M*N. The array is divided into t subarrays of M*(N / t) in a row direction. The serial numbers of the subarrays are in a range of 1 to n. Virtual power ends VHn of sense amplifiers of the subarrays are connected. Virtual power ends VHn between the subarrays are connected by charge transfer switches Tn. M, N, n and t represent natural numbers. The virtual power ends of the sense amplifiers of the subarrays are connected and VHn represents the virtual power ends. The virtual power ends VHn between the subarrays are connected by the charge transfer switches Tn. The compact charge transfer refresh circuit reduces refresh power consumption, obviously reduces refresh time, has a simple control circuit and has no additional area cost.

Description

technical field [0001] The invention belongs to the technical field of memory, and in particular relates to a compact charge transfer refresh circuit and an operation method thereof. Background technique [0002] In recent years, DRAM has been widely used in various consumer electronics products, image and video processing chips, game consoles, etc. Traditionally, the main disadvantage of DRAM in embedded device applications compared to SRAM is: the volatility of storage unit data requires refreshing, which brings additional control logic overhead and data retention power consumption overhead. Among the data retention power consumption, the dynamic power consumption caused by refresh accounts for about 30%, and this part of dynamic power consumption mainly comes from the voltage swing caused by the read and write operations of the unit on the bit line. [0003] In order to reduce the data retention power consumption of DRAM, the traditional scheme divides several groups of ...

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Problems solved by technology

[0008] In addition, since an array access operation is divided into multiple sequential sub-array access operations to perform charge transfer operations between bit lines or arrays, the time for an array access operation becomes longer.

Consider a logical row refresh such as figure 1 and 2 , in the later stage of stage (2) and stage (3), the charge on the parasitic capacitance Cp of sub-array A is in a holding state and has not been transferred, and at this time sub-array B has not yet started the refresh operation, so this period of time becomes a row Redundant time for refresh operations and correspondingly reduced data accessibility of the memory

[0009] Another traditional charge transfer refresh method (Patent Publication No. CN1898748A) proposes a method for repeatedly circulating charges between multiple arrays, but still has the following deficiencies: (1) complex switches need to be set up between multiple arrays The corresponding mechanism requires a complex inductive switch controller, and the area utilization efficiency is not high; (2) The charge transfer refresh steps between multiple arrays in the same row are loose, the row refresh time is long, and the data accessibility of the memory is not high.

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