Memory refresh compensation method and device, compensation circuit and memory device

Abstract

The invention discloses a memory refresh compensation method and device, a compensation circuit and a memory device, and the method comprises the steps: respectively carrying out the statistics of data storage errors in each storage region through multiplexing an error reporting signal generated by an ECC module of each storage region; detecting whether the accumulated error number of each storage area reaches a preset threshold value or not, and determining the storage area with the accumulated error number reaching the preset threshold value as a target storage area; adjusting the number of synchronous refresh lines of the target storage area from a default line number to a set line number, starting counting of refresh instructions at the same time, and resetting the current error statistical number corresponding to the target storage area; and when the accumulated number of the refresh instructions reaches the target value, recovering the synchronous refresh line number of the target storage area to the default line number, so that refresh compensation can be carried out for the storage area with the data failure risk, and the problem of retention of the DRAM storage array can be improved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a memory refresh compensation method, device, compensation circuit and storage device. Background technique [0002] Charge leakage of storage cells of DRAM (Dynamic Random Access Memory, dynamic random access memory) is an inevitable problem, and periodic refreshing is required to ensure that data information in the storage cells is not lost. Due to this characteristic of DRAM, DRAM memory is vulnerable to the threat of bit flip attack ROW HAMMER, that is, multiple switching operations on the same word line (worldline, WL for short), will cause the storage cells on adjacent WL to have the risk of charge leakage and consequences leading to failure. Moreover, storage units with weaker data retention performance (retention) in the storage array are more likely to fail, and need to be refreshed in time before the maximum access times MAC arrives to reduce failure to a certain extent...

AI Technical Summary

Problems solved by technology

Due to this characteristic of DRAM, DRAM memory is vulnerable to the threat of bit flip attack ROW HAMMER, that is, multiple switching operations on the same word line (worldline, WL for short), will cause the storage cells on adjacent WL to have the risk of charge leakage and consequences, leading to failure

Moreover, storage units with weak data retention performance in the storage array are more likely to fail, and need to be refreshed in time before the maximum number of accesses MAC arrives to reduce the failure to a certain extent

[0003] In addition, the charge retention time of memory cells in a memory array is strongly related to temperature, and leakage current is more likely to cause memory failure at high temperatures

Therefore, high temperature easily leads to increased leakage, and DRAM storage arrays are more prone to retention problems, which brings reliability and stability risks to the system-in-chip (SIP) work.

Especially for DRAM memory in the form of 3D packaging, more interconnection wires and more layers of stacked chips in the chip lead to complex thermal distribution and thermal characteristics in the chip, and the retention problem caused by the influence of temperature is more significant

[0004] At present, for the retention problem of DRAM storage arrays, the common solution is to detect and correct data storage errors through on-chip ECC (Error Checking and Correcting, error checking and correction), but the ECC error correction capability is limited. When the retention failure is more, It cannot be corrected, resulting in a large risk of data failure in the DRAM storage array

Images