13 results about "Charge transfer switch" patented technology

The invention provides a global shutter pixel structure, a semiconductor image sensor and a control method. The global shutter pixel structure comprises an optical unit, a signal reading circuit, a signal storage circuit and a signal output circuit, the signal reading circuit comprises a charge transfer switch, a reset switch and a first source follower, the reset switch is coupled between the suspension node and a reset signal end, the reset signal end provides a reset signal, the charge transfer switch is coupled between the optical unit and the suspension node, and the first source follower is coupled between the optical unit and the suspension node. The first source follower is coupled between the voltage conversion signal end and the first node. Compared with the prior art, the global shutter pixel structure provided by the embodiment of the invention has the advantages that a pre-charging tube coupled between the first node and the grounding end is omitted, and global exposure can still be realized. The number of pre-charging tubes near the optical unit is reduced, so that the light sensing area of the optical unit is increased to a certain extent, the light sensitivity is improved, and the image quality is improved.

Example embodiments relate to matrix-vector multiplications based on charge-summing memory cell strings. An example in-memory compute device for performing analog multiply-and-accumulate operations on a set of data inputs and a set of weight inputs includes a string of serially connected memory cells formed over a semiconductor channel structure, a source junction controllably connectible to one end of the string of memory cells via a string select switch, a readout circuit including a sense node controllably connectible to one end of the string of memory cells via a charge transfer switch, and control circuitry. The control circuitry is configured to apply pass mode signals, data input signals, and stop signals sequentially according to each memory cell's position along a string. The control circuitry is also configured to enable the string select switch and the charge transfer switch.

Multi-stage charge pumps use a modular structure in which each stage include a pair of legs, or current paths, between the stage input and the stage output. Each leg includes a stage boosting capacitor having a first plate connected to the current path and a second plate connected to receive one of a pair of non-overlapping clock signals. Each leg has an NMOS charge transfer switch connected between the stage input and the first plate of the stage boosting capacitor and a PMOS charge transfer switch connected between the first plate of the stage boosting capacitor and the stage output. To reduce charge pump area, the NMOS and PMOS charge transfer switches are formed to have a same resistance value when in an on state, where to achieve this the NMOS charge transfer switches are formed with wider control gates than the PMOS charge transfer switches.

The application provides a capacitive touch detection circuit, method and device, wherein the capacitive touch detection circuit comprises a touch electrode, a charge transfer circuit, a voltage detection circuit and a control circuit, the voltage detection circuit is provided with multiple reference voltages, the control circuit controls the charge transfer switch to repeatedly perform charging, charge transfer and charge clearing within a preset number of clock cycles, and the state of a level signal output by the voltage detection circuit is acquired; when m first level signals are acquired within multiple continuous preset numbers of clock cycles, it is determined that a touch operation occurs; otherwise, it is determined that no touch operation occurs; through the mechanism of 'continuous multiple N period confirmation', false triggering caused by instantaneous interference pulses, power supply noise, ESD interference and the like can be effectively filtered out, and through flexible configuration of the value of m, the sensitivity and anti-interference performance can be adjusted.

The application belongs to the technical field of photoelectric detection, and particularly relates to a high-dynamic-range photoelectric detector and a photoelectric image sensor. Mainly comprising: a photodiode (PPD), a diffusion node (FD), a reset switch (RST) and a charge transfer switch (TX). A control device controls these switches to generate initial linear mode (LIN) and logarithmic mode (LOG) response signals of the photoelectric detection element. The control device performs two consecutive exposures on the photodiode with two different working parameters, and a calculation device receiving corresponding signals generates a unified logarithmic response signal by considering the slopes (K1; K2) of the responses and the offsets (OS1; OS2) between the signals.

Multi-stage charge pumps use a modular structure in which each stage include a pair of legs, or current paths, between the stage input and the stage output. Each leg includes a stage boosting capacitor having a first plate connected to the current path and a second plate connected to receive one of a pair of non-overlapping clock signals. Each leg has an NMOS charge transfer switch connected between the stage input and the first plate of the stage boosting capacitor and a PMOS charge transfer switch connected between the first plate of the stage boosting capacitor and the stage output. To reduce charge pump area, the NMOS and PMOS charge transfer switches are formed to have a same resistance value when in an on state, where to achieve this the NMOS charge transfer switches are formed with wider control gates than the PMOS charge transfer switches.

The present invention discloses a photodetector digital integration pixel circuit, specifically a digital integration charge-to-digital conversion circuit that increases charge storage capacity and improves linearity. The circuit comprises a photodetector, an injection tube, an integration capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generating circuit, a charge storage switch, a charge transfer switch, and a unit charge storage capacitor. By using a unit charge storage capacitor and two switches connected thereto, when current integration triggers comparator flipping, the unit charge Qo is used to replenish the charge discharged from the integration capacitor, replacing the traditional digital integration method of resetting voltage. This avoids the influence of the comparator's decision voltage and delay time, and improves the linearity of the charge-to-digital conversion.

In accordance with an embodiment, a method of operating a buck-boost power supply includes operating the buck-boost power supply in a buck mode by providing a PWM signal to a first half-bridge circuit, and turning on a charge transfer switch coupled between a first boosted supply node of a second driver circuit coupled to the first half-bridge circuit and a second boosted supply node of a second driver circuit coupled to a second half-bridge circuit when a voltage between the second boosted supply node and an output of the second half-bridge circuit is below a first threshold; and operating the buck-boost power supply in a boost mode by providing a PWM signal to the second half-bridge circuit, and turning on the charge transfer switch when the voltage between the first boosted supply node and an output of the first half-bridge circuit is below a second threshold.

The invention relates to a photodetector element which comprises a photodiode (PPD), a linked broadcasting node (FD), a controlled recovery switch (RST) able to impose a voltage on the broadcasting node, and a charge transfer switch (TX) able to transfer the charge accumulated in the photodiode to the linked broadcasting node. A control device controls the switches to generate a response of the photodetection element, which response has a linear phase (LIN) followed by a logarithmic phase (LOG). The control device generates two exposures of the photodiode with two different operating parameters, and a computing device that receives the corresponding signals generates a logarithmic unified response signal taking into account a gradient (K1; K2) of the response as well as an offset (OS1; OS2) between the signals.

The present invention discloses a digital integrating charge-digital conversion circuit and a digital pixel circuit for a photodetector. In particular, a digital integrating charge-digital conversion circuit with an increased charge storage capacity and improved linearity is provided. The circuit consists of an injection tube / current source, an integrating capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generation circuit, a charge storage switch, a charge transfer switch, and a unit charge storage capacitor, etc. By using a unit charge storage capacitor and two switches connected thereto, when the current integrates to trigger the comparator to flip, the charge discharged from the integrating capacitor is supplemented with a unit charge Qo, replacing the traditional way of resetting the voltage in digital integration, avoiding the influence of the comparator decision voltage and delay time, and improving the linearity of charge-digital conversion.

A photodetector element comprises a photodiode (PPD) exposed to radiation, a bound scattering node (FD) that converts a change in photoelectric charge in the photodiode into a voltage, a controlled recovery switch (RST) capable of applying a voltage to the scattering node, and a charge transfer switch (TX) capable of transferring the charge accumulated in the photodiode to the bound scattering node. A control device operates the switches to generate a response from the photodetector element, exhibiting an initially linear phase (LIN) followed by a logarithmic phase (LOG), with a potentially indeterminate transition (X) between these phases.According to the invention, the control device generates two exposures of the photodiode with two different operating parameters, and a computing device receiving the two corresponding signals as input generates a unified logarithmic response signal over the entire response range from a combination of the two signals, taking into account on the one hand a slope (K1; K2) of the logarithmic response and on the other hand an offset (OS1; OS2) between the two signals. This is particularly applicable to high dynamic range, low noise matrix image sensors. (Fig. 8).

A charge pump with a programmable architecture generates a deeper negative voltage to reduce chip area requirements and lower current consumption at chip-level. A set of serially connected charge transfer switches are connected between an input node, that can be set at ground or other low voltage, and an output node providing the negative voltage. Stage capacitors each have one plate connected between a pair of the charge transfer switches and a second plate receiving one of a pair of non-overlapping clock signals having an amplitude of the charge pump supply level. The charge transfer switches receive control signals to be alternately on or off and, when off, the output of the charge transfer switch is shorted to its control gate. Different input voltage levels can be selected and used to pre-charge the control gate of the first of the charge transfer switches to provide different output nodes.

The application generally discloses systems and methods of generating a voltage waveform having an amplitude three times an input voltage amplitude using a plurality of low voltage (LV) triple well (TWL) N-type field effect devices. The method includes: receiving a first input voltage at a first input of a double switch charge transfer switch (CTS) circuit; applying a 2× kick voltage to a first capacitor coupled to a first portion of the double switch CTS circuit, the first capacitor configured to discharge a kick voltage to a source of a first LV TWL N-type field effect device; and applying a 1× kick voltage to a second capacitor coupled a second portion of the double switch CTS circuit, the second capacitor configured to discharge a kick voltage to a source of a second LV TWL N-type field effect device.