31 results about "Charge transfer switch" patented technology

A circuit comprising a first switch for sampling a differential signal and a second switch for level-shifting the sampled differential signal is disclosed. The first and second switches are cross-coupled to cancel a charge injected between the first and second switches and for linearizing the charge transfer; and a capacitor coupled is between the first and second switches. A circuit in accordance with the present invention adds an extra sampling switch to the sampling circuit and an extra charge-transfer switch in the level-shifting circuit. By cross-coupling these extra switches, the result is a cancellation of the charge-injection, and thus linearizing the charge transfer.

In addition to an input terminal, an output terminal, a ground terminal, a plurality of external terminals, and a plurality of charge transfer switches, a semiconductor integrated circuit device has a step-up factor switching terminal. Here, the plurality of charge transfer switches each have a common contact connected to corresponding one of the plurality of external terminals and two selection contacts alternatively connected to the common contact, and one of the selection contacts of the plurality of charge transfer switches is connected to the step-up factor switching terminal, and each of the other selection contacts is connected to one of the input terminal, the output terminal, the ground terminal, and the rest of the other selection contacts. With this configuration, it is possible to make the semiconductor integrated circuit device versatile so that it can be used to form charge pump circuits having different step-up factors.

A charge pump provides high boosting efficiency with low power loss even with a heavy load. Plural charge transfer switches are connected in series forming two lines of charge transfer circuits operated by out-of-phase clock signals. Capacitors are connected to each of nodes in the charge transfer circuits. The charge transfer circuits include a first control unit, a second control unit, and a voltage comparison output unit. The second control unit includes a switch unit configured to selectively feed a signal from a previous-stage node or a later-stage node to the gate of a charge transfer switch in the second control unit, depending on the phase of the clock signal.

A power supply circuit has: a DC / DC converter (M11, M12, L11, C11) which steps down an input voltage Vin to generate an output voltage Vout1 by rectifying and smoothing a pulsing switched voltage Vsw generated by turning on and off output switches (M11 and M12); and a charge pump (M11-M14, C12, C13) which steps up the input voltage Vin to generate an output voltage Vout2 by repeating charging and discharging of a charge accumulation capacitor (C12) by turning on and off charge transfer switches (M11-M14). First end of the charge accumulation capacitor is connected to a terminal from which the switched voltage Vsw is outputted. The output switches are also used as part of the charge transfer switches.

The invention discloses a charge transfer type analog count reading circuit based on pulse rising edge triggering. The circuit comprises 13 MOSFET transistors, an integral capacitor and a parasitic capacitor. The MP1 and MP2 are a charge injection switch and a charge transfer switch and are used for controlling generation and transfer of a charge packet. The parasitic capacitor Cgd bridged between a gate and a drain of the MP1 couples an input avalanche pulse signal into the drain of the MP1. The MP4 and MN1 form a reset circuit which is used for discharging charges stored by the integral capacitor. The MP6, MP7, MP8, MN2, MN3 and MN4 form a unit gain amplifier which is used for preventing a voltage of the integral capacitor from being influenced by electric leakage of the MOSFET transistor connected with the integral capacitor C. The MP3 is a source follower transistor. The MP5 is a load. The MP9 is a lien selection transistor. The voltage on the integral capacitor C is read to an external circuit through the MP3 and the MP9. According to the analog count reading circuit, a wide count range can be realized, moreover, an area of SPAD array detector pixel units can be reduced, and the density of an SPAD array detector is improved.

The invention relates to an analog front end detection circuit used for a giant magneto-resistive (GMR) biosensor. The circuit comprises a bandgap reference voltage source, a sensor voltage generating circuit, a 5bit reference voltage generating circuit, a charge transfer switched capacitor sampling / holding circuit and a pipelined analog-to-digital converter. The analog front end detection circuit has the following beneficial effects: the methods of single chip total integration and voltage detection are adopted, thus effectively extracting the weak voltage signals in the GMR biosensor; the charge transfer switched capacitor sampling / holding circuit is utilized to sample the detection voltage of the resistor array of the GMR biosensor and reasonably amplify the detection voltage to the input voltage range of the analog-to-digital converter; and finally, the analog-to-digital converter is used for outputting the digital detection results.

The invention belongs to the technical field of memories and especially relates to a compact charge transfer refresh circuit and a refresh method thereof. The compact charge transfer refresh circuit comprises an array of M*N. The array is divided into t subarrays of M*(N / t) in a row direction. The serial numbers of the subarrays are in a range of 1 to n. Virtual power ends VHn of sense amplifiers of the subarrays are connected. Virtual power ends VHn between the subarrays are connected by charge transfer switches Tn. M, N, n and t represent natural numbers. The virtual power ends of the sense amplifiers of the subarrays are connected and VHn represents the virtual power ends. The virtual power ends VHn between the subarrays are connected by the charge transfer switches Tn. The compact charge transfer refresh circuit reduces refresh power consumption, obviously reduces refresh time, has a simple control circuit and has no additional area cost.

Provided are a charge transfer switch circuit for selectively controlling body bias voltage of a charge transfer device, and a boosted voltage generating circuit having the same. The charge transfer switch circuit may include a capacitor whose voltage is boosted based on first and second control signals, a first transistor connected between a supply voltage and the capacitor and having a gate receiving a precharge signal, a second transistor connected between a first node and a second node and having a gate connected to a terminal of the capacitor, a third transistor connected between the first node and a bulk voltage of the second transistor and having a gate receiving the first control signal, and a fourth transistor connected between the bulk voltage of the second transistor and a ground voltage and having a gate receiving the second control signal.