Memory refresh adjusting method and device, adjusting circuit and memory device

Abstract

The invention discloses a memory refresh adjustment method and device, an adjustment circuit and a memory device, and the method comprises the steps: respectively carrying out the statistics of data storage errors in each storage region through multiplexing an error reporting signal generated by an ECC module of each storage region; detecting whether the accumulated error number of each storage area reaches a preset threshold value or not , and determining the storage area with the accumulated error number reaching the preset threshold value as a target storage area; adjusting the refresh control frequency of the target storage area from a default frequency to a set frequency, starting a preset timer at the same time, and resetting the current error statistical quantity corresponding to the target storage area; and recovering the refresh control frequency of the target storage area to the default frequency until the timing time reaches the preset duration. In this way, the refreshing efficiency of the storage area with the data failure risk can be adjusted, and the problem of retention of the DRAM storage array can be improved.

Description

technical field [0001] The present invention relates to the technical field of memory, in particular to a memory refresh adjustment method, device, adjustment circuit and storage device. Background technique [0002] DRAM (Dynamic Random Access Memory, dynamic random access memory) is stored with capacitors. Even if it is powered on, information will be lost as time and temperature change. Therefore, it must be refreshed every once in a while. This time is called refresh. cycle. [0003] The charge retention time of memory cells in a DRAM memory array is strongly related to temperature, and leakage current is more likely to cause memory failure at high temperatures. Therefore, high temperature easily leads to increased leakage, and DRAM storage arrays are more prone to retention problems, which brings reliability and stability risks to the system-in-chip (SIP) work. Especially for DRAM memory in the form of 3D packaging, more interconnection lines and more layers of stacke...

AI Technical Summary

Problems solved by technology

[0003] The charge retention time of memory cells in a DRAM memory array is strongly correlated with temperature, and leakage current is more likely to cause memory failure at high temperatures

Therefore, high temperature easily leads to increased leakage, and DRAM storage arrays are more prone to retention problems, which brings reliability and stability risks to the system-in-chip (SIP) work.

Especially for DRAM memory in the form of 3D packaging, more interconnection wires and more layers of stacked chips in the chip lead to complex thermal distribution and thermal characteristics in the chip, and the retention problem caused by the influence of temperature is more significant

[0004] At present, for the retention problem of DRAM storage arrays, the common solution is to detect and correct data storage errors through on-chip ECC (Error Checking and Correcting, error checking and correction), but the ECC error correction capability is limited. When the retention failure is more, It cannot be corrected, resulting in a large risk of data failure in the DRAM storage array

Images