Manufacturing method of multi-gate fin field effect transistor
A fin-type field effect transistor and fin ray technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as unstable drain current, unbalanced series resistance, and difficulty in centering the gate. Achieve the effect of solving the unbalance of series resistance, ensuring device performance and stable drain current
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Embodiment 1
[0055] Figure 1a ~ Figure 1g It is a process flow diagram of Embodiment 1 of the method for manufacturing a multi-gate fin field effect transistor according to the present invention. The method is suitable for manufacturing a multi-gate FinFET. The method of this embodiment may include:
[0056] Step 11, forming a channel layer and a gate dielectric layer on the substrate;
[0057] Specifically, such as Figure 1a As shown, a channel layer 102 is formed on a substrate 101 , and a gate dielectric layer 103 is formed on the channel layer 102 . Wherein, the channel layer 102 may deposit a silicon layer on the substrate, and form the channel region of the FinFET by ion implantation, or directly form the channel layer 102 on the silicon substrate by ion implantation, It can be selected according to the actual process requirements. The gate dielectric layer 103 can grow silicon dioxide (SiO2) on the channel layer 102 using a thermal oxidation process. 2 ) to form a gate dielectr...
Embodiment 2
[0075] figure 2 It is the process flow chart of Embodiment 2 of the method for preparing a multi-gate fin field effect transistor of the present invention. In this embodiment, on the basis of the above embodiments, forming a channel layer on the substrate includes: using epitaxy on the substrate. The process forms a first silicon layer and a second silicon layer as the channel layer.
[0076] Such as figure 2 As shown, the first silicon layer 201 is formed on the substrate 101 by an epitaxial process, and the first silicon layer 201 is a silicon layer with an ion concentration. Taking the production of a P-type FinFET as an example, the first silicon layer 201 can be With boron ion B + The silicon layer is used for threshold voltage adjustment; on the first silicon layer 201, the epitaxial process is used to epitaxy the second silicon layer 202 with ion concentration. Taking P-type FinFET as an example, the ions of the second silicon layer 202 can be for B + , its doping...
Embodiment 3
[0080] Figure 3a~Figure 3e It is the process flow chart of Embodiment 3 of the method for manufacturing a multi-gate fin field effect transistor of the present invention. On the basis of the above embodiments, this embodiment forms an amorphous silicon layer on the substrate, and etches Etching the amorphous silicon layer to form at least one fin comprises:
[0081]Step 31, forming a second protective layer on the substrate by using an epitaxial process, and etching the second protective layer by using a patterning process to form a fin pattern;
[0082] Specifically, such as Figure 3a as shown, Figure 3a In order to produce a cross-sectional view along the XZ plane during the multi-gate FinFET process, a second protective layer is epitaxially formed on the substrate on which the gate dielectric layer 103 is formed, and the second protective layer is etched by a patterning process to form a Figure 3a Fin ray pattern 301 is shown. Wherein, the etching in the patterning ...
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Abstract
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